PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 172

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

SQC
SQW
1)
4.7.8
MASKS
Value after reset: FF
Bit 3..0
Data Sheet
Register SQRR stays valid as long as no code change has been received.
7
1
MASKS - Mask S-Transceiver Interrupt
S/Q-Channel Change
0 =
1 =
S/Q-Channel Writable
0 =
1 =
Mask bits
0 = The transceiver interrupts LD, RIC, SQC and SQW are enabled
1 = The transceiver interrupts LD, RIC, SQC and SQW are masked
1
inactive
A change in the received 4-bit Q-channel has been detected. The
new code can be read from the SQRx bits of registers SQRR within
the next multiframe
SQRR register.
inactive
The S channel data for the next multiframe is writable.
The register for the S bits to be transmitted has to be written within
the next multiframe. This bit is reset by writing register SQXR.
This timing signal is indicated with the start of every multiframe.
Data which is written right after SQW-indication will be transmitted
with the start of the following multiframe. Data which is written
before SQW-indication is transmitted in the multiframe which is
indicated by SQW.
SQW and SQC could be generated at the same time.
H
1
1)
1
read/write
. This bit is reset by a read access to the
158
LD
RIC
Register Description
PEF 82912/82913
Address:
SQC
2001-03-30
SQW
0
39
H