WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet
WG82578DM S LGY6
Specifications of WG82578DM S LGY6
Related parts for WG82578DM S LGY6
WG82578DM S LGY6 Summary of contents
Page 1
... Smart speed operation for automatic speed reduction on faulty cable plants — PMA loopback capable (no echo cancel) 1. Refer to the latest Intel® 82578 Specification Update for more details. 2. The MAC is incorporated into the Intel June 2010 Advanced cable diagnostics ...
Page 2
... Intel Corporation (“Intel”). In the event that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel. ...
Page 3
... Overview ................................................................................................ 6 2.4 Transitions between SMBus and PCIe interfaces ...................................................... 8 2.4.1 Switching from SMBus to PCIe ................................................................... 8 2.4.2 Switching from PCIe to SMBus ................................................................... 8 2.5 Intel® 5 Series Express Chipset/82578 – SMBus/PCIe Interconnects.......................... 9 3.0 Pin Interface ........................................................................................................... 11 3.1 Pin Assignment ................................................................................................. 11 3.1.1 Signal Type Definitions............................................................................ 11 3.1.2 PCIe Interface Pins (8)............................................................................ 12 3 ...
Page 4
... Basic Configuration Software Words ........................................................ 104 ® 9.4 Intel 5 Series Express Chipset/82578 NVM Contents........................................... 106 ® 10.0 Intel 5 Series Express Chipset MAC Programming Interface................................. 107 10.1 Register Byte Ordering ..................................................................................... 107 10.2 Register Conventions ....................................................................................... 108 10.2.1 PCI Configuration and Status Registers - CSR Space.................................. 109 11 ...
Page 5
... Datasheet—82578 GbE PHY 11.4 I/O DC/AC Parameters ..................................................................................... 165 11.4.1 3.3 Vdc DC/IO ..................................................................................... 165 11.4.2 2.5 Vdc/IO .......................................................................................... 166 11.4.3 Input Buffer Only ................................................................................. 167 11.4.4 SMBus AC I/O...................................................................................... 168 11.4.5 PCIe DC/AC Specifications ..................................................................... 168 11.5 Discrete/Integrated Magnetics Specifications....................................................... 171 11.6 Oscillator/Crystal Specifications......................................................................... 172 12 ...
Page 6
... Removed old section 8. • Updated section 10.3.1.11 (bit 12 and 13 desctiptions). • Updated figure 1. • Updated table 2. • Updated section 7.4 and 10.3.1.2 (added Intel® 5 Series Express Chipset references). • Added power sequencing note to section 5.3.2. February 2010 2.2 • Updated section 6.4.2.2 (added Windows* 7 reference). ...
Page 7
... Updated Figure 1 (removed ferrite beads from diagram). • Updated Sections 1.2 (added note), 2.2 (added note), 2.3 (added note), and 7.2.2. April 2008 0.7 Added a discrete/integrated magnetics specifications table to Section 7.0. Mar 2008 0.6 Major revision (all sections). Jan 2008 0.5 Initial release (Intel Confidential). vii ...
Page 8
... Overview The 82578 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Intel (MAC) through a dedicated interconnect. The 82578 supports operation at 1000/100/ 10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802 ...
Page 9
... Introduction—82578 GbE PHY Crystal Testability Power Figure 1. 82578 Block Diagram 1.3 Main Flows The 82578 main interfaces are PCIe and SMBus on the host side and the MDI interface on the link side. Transmit traffic is received from the MAC device through either PCIe or SMBus on the host interconnect and then transmitted on the MDI link ...
Page 10
... Intel Corporation ® • Intel 82578 Schematic and Layout Checklists, Intel Corporation ® • Intel 82578 MDI Differential Trace and Power Loss Calculators, Intel Corporation 1.5 Product Codes Table 1 lists the product ordering codes for the 82578 GbE controller. Refer to the ® ...
Page 11
... Introduction—82578 GbE PHY 1.6 Product Matrix Method of enabling/disabling features in SKUs Link Speed Platform Desktop Gigabit Desktop Performance Segment Description Device ID 82578 for Corporate 10EF Corporate 82578 for X Consumer 10F0 Consumer Extended ...
Page 12
... PCIe Interface Signals The signals used to connect between the MAC and the PHY in this mode are: • Serial differential pair running at 1.25 Gb/s for Rx • Serial differential pair running at 1.25 Gb/s for Tx • 100 MHz differential clock input to the PHY running at 100 MHz • ...
Page 13
... Chipset. No other device (like an external BMC) can be connected to SMLink0 when the 82578 is connected to the Intel 2.3.1 Overview SMBus is used as an interface to pass traffic between the 82578 and the Intel Express Chipset when the system low power state (Sx state). The interface is also used to enable the Intel as passing in-band information between them. ...
Page 14
... ACKs, NACKs, STARTs, or STOPs) in the SMBus transaction. The polynomial for this CRC-8 is The PEC calculation is reset when any of the following occurs: • A STOP condition is detected on the host SMBus • An SMBus hang is detected on the host SMBus • The SMB_CLK is detected high for ~50 µs 7 82578 GbE PHY—Interconnects ...
Page 15
... PE_RST_N signal is high. Switching the communication to SMBus is only needed to enable host wake up in low power states and is controlled by the Intel® 5 Series Express Chipset. The switching from PCIe to SMBus is done when the PE_RST_N signal is low. ...
Page 16
... Intel® 5 Series Express Chipset/82578 – SMBus/PCIe Interconnects The 82578 can be connected to any x1 PCIe port in Intel The PCIe port that connects to the 82578 is selected by PCHSTRP9, bits [11:8] in the SPI Flash descriptor region. For more information on this setting, please refer to the ® ...
Page 17
... Interconnects—82578 GbE PHY Note: This page intentionally left blank. 10 ...
Page 18
... The 82578 is packaged in a 48-pin package with a 0.4 mm lead pitch. There are 48 pins on the periphery and a die pad (Exposed Pad*) for ground. Note: Refer to the reference schematics for pin connection details. Contact your Intel representative for access. 3.1.1 Signal Type Definitions ...
Page 19
... Pin Interface—82578 GbE PHY 3.1.2 PCIe Interface Pins (8) Pin Name Pin # PE_RST_N 36 PETp 38 PETn 39 PERp 41 PERn 42 PE_CLKP 44 PE_CLKN 45 CLK_REQ_N 48 3.1.3 SMBus Interface Pins (2) Pin Name Pin # SMB_CLK 28 SMB_DATA 31 1. AUX power means the power rail is available in all power states including transitions and Sx states with Wake on LAN (WoL) enabled ...
Page 20
... PHY Pins (14) 3.1.5.1 LEDs (3) This table lists the functionality of the LED output pins. Refer to the Intel Family Platform Design Guide (PDG) for LED connection details. Pin Name Pin # LED0 26 LED1 27 LED2 25 3.1.5.2 Analog Pins (11) Pin Name Pin# MDI_PLUS[0] 13 MDI_MINUS[0] 14 MDI_PLUS[1] ...
Page 21
... Pin Interface—82578 GbE PHY 3.1.6 Testability Pins (5) Pin Name Pin # JTAG_TCK 35 JTAG_TDI 32 JTAG_TDO 34 JTAG_TMS 33 TEST_EN 30 Note: The 82578 uses the JTAG interface to support XOR files for manufacturing test. BSDL is not supported. 3.1.7 Power Pins (13) Pin Name Pin # 8, 11, 16, 22, AVDD1P2 ...
Page 22
... Package Type and Mechanical The 82578 mm, 48-pin QFN Halogen Free, Pb Free package with a pad size of 3. 3.80 mm. Figure 3. Package Dimensions 15 82578 GbE PHY—Package Notes: Controlling Dimension - Millimeter Reference Document - JEDEC MO-220 Tolerance Requirement for D1/E1: +/- 0.1 mm 3.80 3.95 0.144 0.150 3 ...
Page 23
... Package—82578 GbE PHY 4.2 Package Electrical and Thermal Characteristics The thermal resistance from junction to case, qJC, is 15.1 ×C/Watt. The thermal resistance from junction to ambient, qJA follows: 4-layer PCB, 85 degrees ambient. Air Flow (m/s) No heat sink is required. Maximum 119 1 118 2 116 qJA (× ...
Page 24
... C7 10 CTRL1p2 7 9 1.2V 37,46,47 1. 1.2V 8,11,16,40 82578 GbE PHY—Package Magnetic Center Tap 1uf 1uf +3.3V LAN C6 C5 +3.3V LAN BCP69 R3 1. 1.2v • C1, C2,C5 – X5R 10 uF 6.3V • C8, C9 – X5R 4.7uF 6.3V • ...
Page 25
... Package—82578 GbE PHY 4.4 Pinouts (Top View, Pins Down) RSVD_VCC3P3 RSVD_VCC3P3 LAN_DISABLE_N VDD2P5_OUT VDD3P3_IN CTRL_1P2 AVDD1P2 XTAL_OUT XTAL_IN AVDD1P2 Figure 5. 82578 Pinouts Pin 82578 5 48 Pin QFN 6 VCT 0.4 mm pin pitch with Exposed Pad RBIAS Pin 49 - VSS_EPAD PE_RST_N 35 JTAG_TCK 34 JTAG_TDO ...
Page 26
... MDI_PLUS[2] 9 MDI_MINUS[2] 10 AVDD1P2 11 MDI_PLUS[3] 12 MDI_MINUS[3] 25 DVDD1P2 26 PETp 27 PETn 28 AVDD1P2 29 PERp 30 PERn 31 AVDD1P2 32 PE_CLKP 33 PE_CLKN 34 DVDD1P2 35 DVDD1P2 36 CLK_REQ_N 49 82578 GbE PHY—Package Side Pin Number Bottom 13 Bottom 14 Bottom 15 Bottom 16 Bottom 17 Bottom 18 Bottom 19 Bottom 20 Bottom 21 Bottom 22 Bottom 23 Bottom 24 Top 37 Top 38 Top 39 Top 40 Top ...
Page 27
... Package—82578 GbE PHY Note: This page intentionally left blank. 20 ...
Page 28
... Start PCIe training Send link status message PHY starts link auto-negotiation 82578 GbE PHY—Initialization Internal Xosc stabilizes Internal power on reset is de-asserted ® Wait for Intel 5 Series Express Chipset SMBus address valid MDIO registers are initialized by the MAC PHY establishes link ...
Page 29
... Platform power ramps up (3.3 V dc/2.5/1.2 Vdc) 2 XTAL is stable after T 3 Internal Power On Reset triggers T 4 PCIe training if PE reset is de-asserted. 5 Wait for Intel 6 Send Link Status message. 7 MAC configures the 82578. 8 PHY goes through auto-negotiation to acquire link. sec. XTAL after XTAL is stable. Strapping options are latched. ...
Page 30
... Reset 1. Asserting a 3.3 Vdc power on reset should move the PHY out of power down mode. 2. PHY registers (page 0 in MDIO space and any aliases to page 0) are reset during a PHY soft reset. The rest of the 82578’s MDIO space is not reset. 23 Non-PHY ...
Page 31
... Timing Guarantees The 82578 guarantees the following start-up and power state transition related timing parameters. Note: For platform power sequencing requirements for the Intel® 5 Series Express Chipset MAC, refer to the Intel® 5 Series Express Chipset EDS. Table 6. Timing Guarantees Parameter ...
Page 32
... LAN (WoL) enabled Sx WoL disabled 1. Measured power could be higher or lower based on measurement setup and PHY power delivery configuration. 2. Assumes the system is in the Moff state and SLP_LAN# is used to gate PHY power. 25 82578 GbE PHY—Power Management and Delivery 3.3 Vdc 1.8 Vdc ...
Page 33
... An external power supply not dependent on support from the 82578. For example, the platform designer might choose to route a platform-available 1.2 Vdc supply to the 82578. Intel • A discrete LVR solution, where the base current of PNP power transistor is driven by the 82578, while the power transistor is placed externally. ...
Page 34
... Power Up Defined as the period from the time power is applied to the 82578 and until the 82578 powers up its PHY. the 82578 should consume less than ~40 mA during this period. Following the 82578 PHY entering reset, the power-up sequence is considered done and the requirement is removed. ...
Page 35
... Intel Auto Connect Battery Saver (ACBS) ® Intel Auto Connect Battery Saver for the 82578 is a hardware-only feature that automatically reduces the PHY to a lower power state when the power cable is disconnected. When the power cable is reconnected, it renegotiates the line speed following IEEE specifications for auto negotiation ...
Page 36
... Then, with both the monitor off and the network idle, the LAN negotiates to the lowest possible link speed supported by both the PHY and the link partner (typically 10 Mb/s). If the link partner is hard-set to only advertise a certain speed, then the LAN negotiates to the advertised speed ...
Page 37
... For example, if the 82578 advertises 10 Mb/s only and the link partner supports 1000/100 Mb/s only, a 100 Mb/s link is established. LPLU is controlled through the LPLU bit in the PHY Power Management register. The MAC sets and clears the bit according to hardware/software settings. The 82578 auto negotiates with the updated LPLU setting on the following auto-negotiation operation ...
Page 38
... LAN Disable Recommendations LAN_DISABLE_N needs to be connected to the GPIO12/LAN_PHY_PWR_CTRL output of ® the Intel 5 Series Express Chipset. GPIO12 also needs to be configured using Intel Series Express Chipset soft straps as LAN_PHY_PWR_CTRL (bit [20] of PCHSTRP0 register - LAN_PHY_PWR_CTRL/GPIO12. Refer to the Intel Family External Design Specification (Intel 31 82578 GbE PHY— ...
Page 39
... Power Management and Delivery—82578 GbE PHY Note: This page intentionally left blank. 32 ...
Page 40
... The implementation of asymmetric flow control allows for one link partner to send flow control packets while being allowed to ignore their reception. For example, not required to respond to PAUSE frames. 33 82578 GbE PHY—Device Functionality ...
Page 41
... Device Functionality—82578 GbE PHY 7.3.1 MAC Control Frames and Reception of Flow Control Packets Three comparisons are used to determine the validity of a flow control frame match on the six-byte multicast address for MAC control frames or to the station address of the device (Receive Address Register 0). ...
Page 42
... Wake Up The 82578 supports host wake up. This mechanism uses in-band messages to wake the Intel from a sleep state. The host can enable host wake up from the 82578 by setting the Host_WU_Active bit. When this bit is set, after the host transitions to a low power state, the SMBus interface is still active and the wake up indication from the 82578 to ® ...
Page 43
... Note: Once wake up is enabled, the 82578 stops responding to SMBus commands. Host wake up: 1. When a WoL packet/event is detected, the 82578 sends an in-band message to the Intel® 5 Series Express Chipset indicating a host wake up. ® 2. The Intel 5 Series Express Chipset wakes the host. ...
Page 44
... PM_PME message (if configured to). At power up, if the 82578’s wake up functionality is enabled, the APM Enable bits from the NVM are written to the 82578 by the Intel Enable (APME) bits of the Wakeup Control (WUC) register. These bits control the enabling of APM wake up. ...
Page 45
... If a packet passes both the standard address filtering and at least one of the enabled wake up filters, the 82578: • Initiates a the Intel • Sets one or more of the Received bits in the WUS register. Note that more than one bit is set if a packet matches more than one filter. ...
Page 46
... Offset # of Bytes Field Value Action Destination Address Compare Field Value Destination Address Field Destination Address 82578 GbE PHY—Device Functionality Comment Match any pre-programmed address as defined in the receive address Action Comment Compare See previous paragraph. Value Action Comment FF*6 Compare ...
Page 47
... Device Functionality—82578 GbE PHY 7.4.1.3.1.4 Magic Packet Magic packets are defined as follows: — Magic Packet Technology Details - Once the 82578 has been put into Magic Packet mode, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the MAC that this is a Magic Packet frame. A ...
Page 48
... Protocol Address Length 0x04 Compare Operation 0x0001 Compare Sender Hardware Address - Ignore Sender IP Address - Ignore Target Hardware Address - Ignore Target IP Address IP4AT Compare 82578 GbE PHY—Device Functionality Comment MAC Header – processed by main address filter Might match any of four values in IP4AT ...
Page 49
... Device Functionality—82578 GbE PHY 7.4.1.3.1.6 Directed IPv4 Packet The 82578 supports receiving Directed IPv4 packets for wake up if the IPV4 bit (bit 6) is set in the WUFC register. Three IPv4 addresses are supported, which are programmed in the IPv4 Address Table (IP4AT). A successfully matched packet must contain the station’ ...
Page 50
... Compare Field Value Destination Address Source Address Possible VLAN Tag Possible Len/LLC/SNAP Header Type 0x8137 Some IPX Information - IPX Diagnostic Socket 0x0456 82578 GbE PHY—Device Functionality Comment Match value in IP6AT Action Comment Compare Skip Skip Skip Compare IPX Ignore Compare ...
Page 51
... After the page is set to the wake up page, the Address field is no longer translated as reg_addr (register address) but as an instruction. If the given address is in [0..15] range meaning PHY registers, the functionality remains unchanged. There are two valid instructions: Instruction ...
Page 52
... PHY loopback is supported in the 82578. Software or firmware should set the 82578 to the loopback mode (via the MDIC register) writing to the PHY Loopback Control register (address 19). The MAC must be in forced link and in full duplex mode for PHY loopback to operate. The following bits must be configured to enable PHY loopback: CTRL ...
Page 53
... Device Functionality—82578 GbE PHY Note: This page intentionally left blank. 46 ...
Page 54
... When a register number is used for registers 16-21, or 23-28, it refers to the register in page 0. — Register 31 in PHY address 01, is the page register itself and doesn’t belong to any page always written as register 31. • By page and register number — This can be written out as page x, register y, but is often abbreviated x.y • ...
Page 55
... PHY address 01, are divided into pages. Each page has 32 registers. Registers 0-15 are identical in all the pages and are the IEEE defined registers. Register 31 is the page register in all pages of PHY address 01. All other registers are page specific. In order to read or write a register, software should define the appropriate PHY address ...
Page 56
... GbE PHY—Programmer’s Visible State Register Name 0 Control Register 1 Status Register 2 PHY Identifier [18:3] 3 PHY Identifier [19:24] 4 Auto-Negotiation Advertisement 5 Link Partner Ability (Base Page) Base 6 Auto-Negotiation Expansion 7 Next Page Transmit ...
Page 57
... Programmer’s Visible State—82578 GbE PHY Table 9. Address Map 01 770 01 770 01 770 01 770 01 770 01 770 01 776 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 01 800 16 PCIe FIFOs Control/Status 17 PCIe Power Management Control ...
Page 58
... Duplex 10 Mbps Half- 11 Duplex 51 82578 GbE PHY—Programmer’s Visible State Mode HW Rst SW Rst Writing this bit causes immediate PHY reset. Once the operation completes, this bit clears to 0b automatically R/ PHY reset Normal operation. When loopback is active, the transmitter data on TXD loops back to RXD internally. The link breaks when loopback is enabled ...
Page 59
... Organizationally Unique Identifier (OUI), bits [18:3]. Type Default RO 110100b OUI, bits [24:19]. The value is part of the PHY identifier and represents the RO 000100b Device Model Number. The value is part of the PHY identifier and represents the RO 0x2 Device Revision Number. Description Description Description 52 ...
Page 60
... Pause 9 100BASE-T4 100BASE-TX 8 Full-Duplex 100BASE-TX 7 Half-Duplex 10BASE-TX 6 Full-Duplex 10BASE-TX 5 Half-Duplex 4:0 Selector Field R/W Table 15. Link Partner Ability (Base Page) Base PHY Address 02, Page Any, Register 5 Bits Field 15 Next Page 14 Acknowledge 13 Remote Fault Technology 12 Ability Field Asymmetric 11 Pause Pause 10 Capable 100BASE-T4 ...
Page 61
... Programmer’s Visible State—82578 GbE PHY Table 15. Link Partner Ability (Base Page) Base PHY Address 02, Page Any, Register 5 Bits Field 100BASE-TX 8 Full-Duplex Capability 100BASE-TX 7 Half-Duplex Capability 10BASE-T 6 Full-Duplex Capability 10BASE-T 5 Half-Duplex Capability 4:0 Selector Field Table 16. Auto-Negotiation Expansion PHY Address 02, Page Any, Register 6 ...
Page 62
... Table 17. Next Page Transmit PHY Address 02, Page Any, Register 7 Bits Field 12 Acknowledge2 11 Toggle Message/ 10:0 Unformatted Field Table 18. Link Partner Next Page PHY Address 02, Page Any, Register 8 Bits Field 15 Next Page 14 Acknowledge 13 Message Page 12 Acknowledge2 11 Toggle 10:0 Message Unformatted Field Table 19. ...
Page 63
... Master/slave configuration fault detected master/slave configuration fault detected. This register bit is not valid until the PAGE_RECEIVED (bit [1]) of register Auto-Negotiation Expansion is set to 1b Local PHY configuration resolved to the master Local PHY configuration resolved to the slave Local receiver is correct Local receiver is incorrect Remote receiver is correct. ...
Page 64
... Table 22. Function Control 1 PHY Address 02, Page 0, Register 16 Bits Field 15:12 Reserved Assert_ 11 CRS_On_ Transmit 10 Reserved Energy 9:8 Detect 7 Reserved MDI 6:5 Crossover Mode 4:3 Reserved 2 SQE_TEST Polarity 1 Reversal Disable Disable 0 Jabber Table 23. PHY-Specific Status 1 PHY Address 02, Page 0, Register 17 Bits Field 15:14 ...
Page 65
... Programmer’s Visible State—82578 GbE PHY Table 23. PHY-Specific Status 1 PHY Address 02, Page 0, Register 17 Bits Field Copper Link 10 (real time) 9:7 Reserved MDI Crossover 6 Status Smartspeed_ 5 Downgrade Energy Detect 4 Status Transmit_ 3 Pause_Enabled Receive_ 2 Pause_Enabled Polarity (real 1 time) Jabber (real 0 time) Table 24. ...
Page 66
... Table 24. Interrupt Enable PHY Address 02, Page 0, Register 18 Bits Field 8 False Carrier Interrupt Enable FIFO Over/ Underflow Interrupt 7 Enable MDI Crossover Changed Interrupt 6 Enable 5 Smartspeed Interrupt Enable 4 Energy Detect Interrupt Enable 3:2 Reserved 1 Polarity Changed Interrupt Enable R/W 0 Jabber Interrupt Enable Table 25. ...
Page 67
... Programmer’s Visible State—82578 GbE PHY Table 25. Interrupt Status PHY Address 02, Page 0, Register 19 Bits Field 3:2 Reserved 1 Polarity Changed 0 Jabber Table 26. Extended PHY-Specific Control PHY Address 02, Page 0, Register 20 Bits Field 15:11 Reserved 10 aneg_now_qual 9 Rev_aneg_qual 8 Giga_dis_qual 7 Cfg_dis_qual 6 Mr_Itdis 5 Smartspeed_En Mode HW Rst ...
Page 68
... Bypass_ 1 Smartspeed_Timer 0 Reserved Table 27. Receive Error Counter PHY Address 02, Page 0, Register 21 Bits Field 15:0 Receive Error Count RO Table 28. Cable Defect Tester Control PHY Address 02, Page 0, Register 22 Bits Field 15:10 Reserved 9:8 MDI_PAI_Select 7:1 Reserved 0 Enable_Test 61 82578 GbE PHY—Programmer’s Visible State ...
Page 69
... Programmer’s Visible State—82578 GbE PHY Table 29. LED Control PHY Address 02, Page 0, Register 24 Bits Field 15 Disable LED 14:12 LED On Time 11 Force Interrupt 10:8 LED On Time 7:5 Reserved 4:3 LED_LINK Control 2 LED_DUPLEX 1 LED_RX Control 0 Enable_Test Mode HW Rst SW Rst 0b = Enable. R/W 0b Retain 1b = Disable ...
Page 70
... Table 30. Manual LED Override PHY Address 02, Page 0, Register 25 Bits Field 15:12 Reserved 11:10 LED_DUPLEX 9:8 LED_LINK10 7:6 LED_LINK100 5:4 LED_LINK1000 3:2 LED_RX 1:0 LED_TX 63 82578 GbE PHY—Programmer’s Visible State Mode HW Rst SW Rst RO 0x00 00x00 Reserved LED off means LED pin output equals high. ...
Page 71
... Cable Defect Tester Status PHY Address 02, Page 0, Register 28 Bits Field 15:10 Reserved 9:8 Status 7:0 Delta_Time Table 32. Debug Port Address Offset PHY Address 02, Page 0, Register 29 Bits Field 15:6 Reserved 5:0 Address_Offset Table 33. Debug Port Data PHY Address 02, Page 0, Register 30 Bits Field ...
Page 72
... Retain Reserved Mode HW Rst SW Rst Power Hibernate Control Bit R/W 1b Retain 1b = Hibernate enable Hibernate disable PHY wake up by energy detect or wake up pin. R/W 0b Retain 0b = PHY wake up only by energy detect. R/W 1b Retain Reserved 1b = When hibernate, PHY sends NLP pulse and detects signal from cable. ...
Page 73
... Programmer’s Visible State—82578 GbE PHY Table 37. 100BASE-TX Test Mode Register, Address Offset = 0x10 Bits Field 15 TM100_ENA 14:8 Reserved 7 Jitter_test 6 Os_test 5 Dcd_test 4 PMD_LPBK_2 3 PMD_LPBK_1 2 PMA_LPBK_2 1 PMA_LPBK_1 0 PCS_LPBK Table 38. 1000BASE-T Test Mode Register, Address Offset = 0x11 Bits Field 15:1 Reserved 0 Ext_lpbk_1000 Table 39 ...
Page 74
... Bits Field 8:6 Dac_amp_10 5:1 Reserved 0 ecnc_ps_en 67 82578 GbE PHY—Programmer’s Visible State Mode HW Rst SW Rst Control amplitude of transmit signal in 100BT R/W 0x3 Retain mode. R/W 0x0 0 Reserved 1b = ecnc power saving enable. R/W 1b Retain 0b = ecnc power saving disable. Description ...
Page 75
... Wait IPG expires until the Back Pressure In- band bit is cleared Reserved Active Power Down Enable (sD3 Enable) When set to 1b, the Intel® 5 Series Express 0b 6 Chipset needs to enter MAC power down mode. Reserved. This bit is reset by power on reset 1b 5 only ...
Page 76
... If collision threshold is set below 16, this counter won’t increment. This register only increments if transmits are enabled and the 82578 is in half-duplex mode. Table 48. Multiple Collision Count - MCC PHY Address 01, Page 778, Register Bit Type 31:0 RO/V 69 82578 GbE PHY— ...
Page 77
... The behavior of this counter is slightly different in the 82578 relative to the 82542. For the 82578, this counter does not increment for streaming transmits that are deferred due to TX IPG. Table 52. Transmit with No CRS - TNCRS PHY Address 01, Page 778, Register Bit Type 31:0 ...
Page 78
... PCIe Registers Table 53. PCIe FIFOs Control/Status PHY Address 01, Page 770, Register 16) Name Reserved Rx FIFO overflow Reserved Tx FIFO overflow Reserved Table 54. PCIe Power Management Control PHY Address 01, Page 770, Register 17 Name Burst enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved 71 82578 GbE PHY—Programmer’s Visible State ...
Page 79
... Timeouts PHY Address 01, Page 770, Register 21 Name Reserved Reserved Reserved 1. All in-band timeouts are multiplied by 1000 while in SMBus mode. Table 58. PCIe Kstate Minimum Duration Timeout PHY Address 01, Page 770, Register 1 23 Name Reserved EI_min_dur timeout 1. All in-band timeouts are multiplied by 1000 while in SMBus mode. ...
Page 80
... General Registers Table 59. 82578 Capability PHY Address 01, Page 776, Register 19 Name Reserved Reserved 802.1Q & 802.1p Receive Side Scaling 2 Tx and 2 Rx Queues Energy Detect AC/DC Auto Link Speed Connect Reserved Reserved Ability to initiate a team The 82578 Capability register is loaded with the set of capabilities that correspond to the selected the 82578 SKU ...
Page 81
... SMBus Address Valid SMBus Address 1. This register is reset only on internal power on reset. Table 62. Shadow Receive Address Low0 – SRAL0 PHY Address 01, Page 0, Registers 27-28 Attribute Bit(s) RW 31:0 Table 63. Shadow Receive Address High0 – RAH0 PHY Address 01, Page 0, Registers 29 Attribute Bit(s) RW 15:0 RW 17:16 RO 30: ...
Page 82
... Table 64. LED Configuration PHY Address 01, Page 0, Register 30 Name Default Blink rate 0b LED2 Blink 0b LED2 Invert 0b LED2 Mode 110b LED1 Blink 0b LED1 Invert 0b LED1 Mode 111b LED0 Blink 1b LED0 Invert 0b LED0 Mode 100b NOTES: 1. When LED Blink mode is enabled the appropriate Led Invert bit should be set to zero. ...
Page 83
... If the given address is in the [0..15] range, meaning PHY registers, the functionality remains unchanged. There are two valid instructions: 1. Address Set – 0x11 – Wake up space address is set for either reading or writing. ...
Page 84
... PHYADD = The 82578’s address from the MDI register d. REGADD = 0x12 (data cycle for write) e. DATA = YYYY (data to be written to the register) 8.10.2 Host Wake Up Control Status Register Description Table 65. Receive Control – RCTL PHY Address 01, Page 800, Register 0 Attribute Bit( ...
Page 85
... Programmer’s Visible State—82578 GbE PHY Note: All wake up registers (page 800-801 except CTRL and IPAV) are not cleared with PHY reset is asserted only cleared when internal power on reset is de-asserted or when cleared by the software device driver. Note: Access to page 800/801 should be done only in 10 Mb/s and 100 Mb/s. ...
Page 86
... Table 67. Wake Up Filter Control – WUFC PHY Address 01, Page 800, Register 2 Attribute Bit( This register is used to enable each of the pre-defined and flexible filters for wake up support. A value of 1b means the filter is turned on, and a value of 0b means the filter is turned off. 79 82578 GbE PHY—Programmer’s Visible State ...
Page 87
... This register is used to record statistics about all wake up packets received. Note that packets that match multiple criteria might set multiple bits. Writing any bit clears that bit. This register is not cleared when PHY reset is asserted only cleared when internal power on reset is de-asserted or when cleared by the software device driver. Initial ...
Page 88
... Table 69. Receive Address Low – RAL PHY Address 01, Page 800, Registers 16- 4*n (n=0…6) Attribute Bit(s) RW 31:0 1. While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6. Table 70. Receive Address High – RAH PHY Address 01, Page 800, Registers 18-19 + ...
Page 89
... Table 72. Shared Receive Address High – SHRAH PHY Address 01, Page 800, Registers 46-47 + 4*n (n=0…2) Attribute Bit(s) RW 15:0 RO 17:16 RO 30: Table 73. Shared Receive Address High 3 – SHRAH[3] PHY Address 01, Page 800, Registers 58-59 Attribute Bit(s) RW 15:0 RO 17:16 RO 29: Initial Value Receive Address Low (RAL) The lower 32 bits of the 48-bit Ethernet address n (n=0… ...
Page 90
... The IPv4 address table is used to store the three IPv4 addresses for IPv4 request packets and directed IPv4 packet wake ups 3-entry table with the following format: Table 76. IPv6 Address Table – IP6AT PHY Address 01, Page 800, Registers 88-89 + 2*n (n=0…3) Attribute ...
Page 91
... The complete multicast offset options are: 00b 01b 10b 11b Figure 9. Multicast Table Array Algorithm Table 78. Flexible Filter Value Table LSB– FFVT_01 PHY Address 01, Page 800, Registers 256 + 2*n (n=0…127) Attribute Bit(s) RW 7:0 RW 15:8 There are 128 filter values. The flexible filter value is used to store the one value for each byte location in a packet for each flexible filter ...
Page 92
... Flexible Filter Enable bits of the WUFC register (WUFC.FLXn). Table 80. Flexible Filter Value Table – FFVT_45 PHY Address 01, Page 800, Registers 512 + 2*n (n=0…127) Attribute Bit(s) RW 7:0 RW 15:8 Table 81. Flexible Filter Mask Table – FFMT PHY Address 01, Page 800, Registers 768 + n (n=0…127) Attribute Bit( ...
Page 93
... Before writing to the flexible filter length table the software device driver must first disable the flexible filters by writing zeros to the Flexible Filter Enable bits of the WUFC register (WUFC.FLXn). Table 83. Flexible Filter Length Table – FFLT45 PHY Address 01, Page 800, Registers 904 + n (n=0…1) Attribute Bit(s) ...
Page 94
... Descriptor Region is used to define vendor specific information and the location, allocated space, and read and write permissions for each region. The Manageability (ME) Region contains the code and configuration data for ME functions such as Intel Active Management Technology. The system BIOS is contained in the BIOS Region. The ...
Page 95
... Intel representative. 2. The GbE region must be part of the original image flashed onto the part. 3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC register(s) correctly. There are two sets of VSCC registers, the upper (UVSCC) and lower (LVSCC) ...
Page 96
... Protected Range register of the GbE LAN Memory Mapped Configuration registers must be set to their default value of 0x0000 0000. (The GbE Protected Range registers are described in the Intel 5. The sector size of the NVM must equal 256 bytes KB. When a Flash device that uses sector erase is used, the GbE region size must equal 128 KB ...
Page 97
... Network Interface Card (NIC) or LAN on Motherboard (LOM), and thus unique for each copy of the NVM image. The first three bytes are vendor specific - for example, the IA is equal to [00 AA 00] or [00 A0 C9] for Intel products. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). ...
Page 98
... This field is reserved and must be set to 000b. 1b Reserved, must be set to 1b. 0000b These bits are reserved and must be set to 0000b. Auxiliary Power Indication If set and if PM Ena is set, D3cold wake-up is advertised in the Intel 5 Series Express Chipset of the PCI function AUX power AUX power. Power Management Enable (PME-WoL) Enables asserting PME in the PCI function at any power state ...
Page 99
... Reserved, set to 1b. 001b Reserved, set to 001b. Enable PHY Power Down When set, enables PHY power down at DMoff/ and no WoL. This bit is loaded to the PHY Power Down Enable bit in the 0b Extended Device Control (CTRL_EXT) register Enable PHY power down PHY always powered up. ...
Page 100
... Dynamic Clock 0 gating 93 82578 GbE PHY—Non-Volatile Memory (NVM) Default Description PHY Device Type Indicates that the PHY is connected to the MAC and resulted mode of operation of the MAC/PHY link buses. 00b = 82578. 00b 01b = Reserved. 10b = Reserved. 11b = Reserved. 01 Reserved, should be set to 1b. ...
Page 101
... This configuration area also includes the PHY tuning (tuning for IEEE) in the NVM. Since this bit 0b is set default, PHY tuning does not take effect until the LAN driver and/or firmware loads. When disabled, the extended LAN connected device configuration area is ignored. Loaded to the EXTCNF_CTRL register ...
Page 102
... OEM Configuration Defaults (Word 0x17) This word defines the OEM fields for the PHY power management parameters loaded to the PHY Control (PHY_CTRL) register. Bits Name 15 Reserved 14 GbE Disable 13:12 Reserved GbE Disable in 11 non-D0a LPLU Enable in 10 non-D0a LPLU Enable in ...
Page 103
... LED Configuration Defaults (Word 0x18) This NVM word specifies the hardware defaults for the LED Control (LEDCTL) register fields controlling the LED1 (LINK_1000), LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors. Refer to the Intel Schematics for LED connection details. Also, outputs. Note: Due to the architecture of the 82578 the customized LEDs settings are written to the 82578 by the LAN driver ...
Page 104
... Reserved 1 Reserved 0 APM Enable 97 82578 GbE PHY—Non-Volatile Memory (NVM) Mnemonic State / Event Indicated Asserted when either 10 or 1000 Mb/s link is established and maintained. Asserted when either 100 or 1000 Mb/s link is established and maintained. Asserted when any speed link is established and maintained ...
Page 105
... Description 0x0 Reserved, set to 0x0. 0b Enable PLL stop in K1. 0b Enables K0s mode when PHY link speed is 10/100 Mb/s. 0b Enables K0s mode when PHY link speed is 1000 Mb/s. 0b Reserved, set to 0b. 0b When set to 1b enables K1 low power mode. Default Description 0x10EF Reserved ...
Page 106
... Software Accessed Words 9.3.2.1 PXE Words (Words 0x30 Through 0x3E) Words 0x30 through 0x3E (bytes 0x60 through 0x7D) have been reserved for configuration and version values to be used by PXE code. 99 82578 GbE PHY—Non-Volatile Memory (NVM) Default Description 1b Reserved, set to 1b. 0b Reserved, set to 0b ...
Page 107
... The boot agent software configuration is controlled by the NVM with the main setup options stored in word 0x30. These options are those that can be changed by using the Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these settings only apply to Boot Agent software. ...
Page 108
... Word 0x31 contains settings that can be programmed by an OEM or network administrator to customize the operation of the software. These settings cannot be changed from within the Control-S setup menu or the IBA Intel Boot Agent utility. The lower byte contains settings that would typically be configured by a network administrator using the Intel Boot Agent utility ...
Page 109
... Non-Volatile Memory (NVM)—82578 GbE PHY Bit Name 2 DPS 1 DTM 0 DSM Description Disable Protocol Select If set to 1b, no changes to the boot protocol is allowed. The default for this bit is 0b; allow changes to the boot protocol. Disable Title Message If set to 1b, the title message displaying the version of the boot agent is suppressed ...
Page 110
... Flash updated by IBA configuration tools and is not updated or read by IBA. 103 82578 GbE PHY—Non-Volatile Memory (NVM) Description PXE boot agent major version. The default for these bits is 0x1. PXE boot agent minor version. The default for these bits is 0x2 ...
Page 111
... Non-Volatile Memory (NVM)—82578 GbE PHY Table 16. IBA Capabilities Bit Name 15:14 SIG 13:5 Reserved 4 3 EFI 2 Reserved 1 UNDI 0 BC 9.3.2.2 Checksum Word Calculation (Word 0x3F) The Checksum word (Word 0x3F, NVM bytes 0x7E and 0x7F) is used to ensure that the base NVM image is a valid image. The value of this word should be calculated such that after adding all the words (0x00-0x3F) / bytes (0x00-0x7F), including the Checksum word itself, the sum should be 0xBABA ...
Page 112
... The nine-digit Printed Board Assembly (PBA) number used for Intel manufactured Network Interface Cards (NICs) and Lan on Motherboard (LOMs) are stored in a four- byte field. The dash itself is not stored, neither is the first digit of the 3-digit suffix always zero for the affected products. Note that through the course of hardware ECOs, the suffix field (byte 4) is incremented ...
Page 113
... Non-Volatile Memory (NVM)—82578 GbE PHY ® 9.4 Intel 5 Series Express Chipset/82578 NVM Contents This section lists the NVM contents for the Intel 82578. Table 17. LAN NVM Contents Word 0x00:0x02 Ethernet Individual Address 0x03:0x04 Reserved 0x05 Image Version Information 0x06:0x07 Reserved ...
Page 114
... The following listed exceptions use network ordering (also called big endian). Using the previous example, a 16-bit field (such as EtherType) is stored in a CSR in the following manner: Dword aligned or Word aligned DW address ( 107 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface First First Byte 3 Byte 2 0x03 0x02 ... ...
Page 115
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY The following exceptions use network ordering: • All ETherType fields The normal notation as it appears in text books, etc use network ordering. For example, the following MAC address: 00-A0-C9-00-00-00. The order on the network is 00, then A0, then C9, etc ...
Page 116
... GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Table 18. These registers are ordered by Abbreviation Name General Register Descriptions CTRL Device Control Register STATUS Device Status Register STRAP ...
Page 117
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Offset 0x000C0 0x000C4 0x000C8 0x000D0 0x000D8 0x000E0 0x00100 0x00104 0x02008 0x02170 0x02160 0x02168 0x02800 0x02804 0x02808 0x02810 0x02818 0x02820 0x02828 0x0282C 0x02C00 0x02C08 0x05000 0x05008 0x05200-0x0527C 0x05400 + 8*n (n=0…6) 0x05404 + 8*n (n=0… ...
Page 118
... Certain registers maintain an alias address designed for backward compatibility with software written for the previous devices. Registers that have an alias address can be accessed by software at either the new offset or the alias offset recommended that software that is written solely for the Intel 82578 use the new address offset. 111 ® ...
Page 119
... MAC on the asserting edge of the PHY link signal. When asserted, the CTRL.FD bit sets duplex. 0b Reserved. 0b Reserved. 0b Reserved. Reads as 0. 0b0 Reserved. Memory Error Handling Enable (MEHE). When set to 1b, the Intel® Series Express Chipset reaction to correctable and uncorrectable memory errors detection are activated. 1b Reserved. 0x0 Reserved. 0b Reserved. ...
Page 120
... This register's address is also reflected at address 0x00004 for legacy reasons. Neither the software driver nor firmware should use it since it might be unsupported in next generations. 113 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Transmit Flow Control Enable (TFCE). Indicates that the MAC transmits 0b flow control packets (XON and XOFF frames) based on receiver fullness ...
Page 121
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.1.2 Device Status Register - STATUS (0x00008; RO) Bits Attribute 0 RO/V 1 RO/V 3:2 RO/V 4 RO/V 5 RO/V 7:6 RO/V 8 RO/V 9 RW/V/C 10 RW/V/C 18: RO/V 29: RO/SN Reset Description Full Duplex (FD Half duplex Full duplex. Reflects duplex setting of the MAC and/or link. ...
Page 122
... MAC only, if the MAC speed setting has been forced via software (CTRL.SPEED). Speed indications are mapped as shown below: • 00b = 10 Mb/s • 01b = 100 Mb/s • 10b = 1000 Mb/s • 11b = 1000 Mb/s 115 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface ...
Page 123
... Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.1.3 Strapping Option Register - STRAP (0x0000C; RO) This register reflects the values of the soft strapping options fetched from the NVM descriptor in the Intel the MAC following LAN_RST# or global reset (PCI reset assertion). Bit(s) Type ...
Page 124
... GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Driver loaded (DRV_LOAD). This bit should be set by the driver after it was loaded and cleared when the driver unloads or after a soft reset. The ...
Page 125
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.1.5 MDI Control Register - MDIC (0x00020; RW) Bits Type 15:0 RW/V 20:16 RW/V 25:21 RW/V 27:26 RW/V 28 RW/V 29 RW This register is used by software to read or write Management Data Interface (MDI) registers in the 82578. ...
Page 126
... Enable dynamic clock stop. When this bit is set to 1b, 0b clk is always ticking. The default value is 0b (hardware and NVM). Invalid Image CSUM. When cleared, this bit indicates to the Intel NVM 0b programming tools (eeupdate) that the image CSUM needs to be corrected. When set the CSUM is assumed to be correct. ...
Page 127
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Bits Type 9:7 RW/SN 10 RW/SN 11 RW/SN 12 RW/SN 13 RW/SN 14 RW/SN 15 RW/SN 19:16 RW/SN 20 RW/SN 26:21 RW/SN 27 RW/SN 31:28 RW/SN Reset Description 0x0 Reserved. Enable MDIO Watchdog Timer (MDIOWatchEna). When set to 0b, the 100 ms MDIO watchdog timer is enabled ...
Page 128
... RO 10.2.1.1.9 Flow Control Transmit Timer Value - FCTTV (0x00170; RW) Bit Type 15:0 RW 31:16 RO 121 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0b Reserved. 0b Reserved. 00b Reserved. 0x0 Reserved. Hardware/Software CRC Mismatch Trigger. When set to 1b the MAC ...
Page 129
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY The 16-bit value in the TTV field is inserted into a transmitted frame (either XOFF frames or any PAUSE frame value in any software transmitted packets). It counts in units of slot time. If software needs to send an XON frame, it must set TTV to zero prior to initiating the PAUSE frame ...
Page 130
... RW/SN 1 RW/SN 0 RW/SN 123 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0x0 Reserved. Extended LCD Length. Size (in Dwords) of the extended PHY configuration area loaded from Extended Configuration word 2 in the NVM 0x0 extended configuration area is disabled by the LCD Write Enable field in word 0x14 in the NVM, this length must be set to zero ...
Page 131
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.1.14 PCIE Analog Configuration - PCIEANACFG (0x00F18; RW) Bit Type 0 RW 6:1 RW 31:7 RO 10.2.1.1.15 Packet Buffer Allocation - PBA (0x01000; RW) Bit Type 4:0 RW 15:5 RO 20:16 RO 31:21 RO This register sets the on-chip receive and transmit storage allocation ratio. ...
Page 132
... RO 23:16 RW 31:24 RW 125 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Correctable Error Count (Corr_err_cnt). This counter is incremented every 0x0 time a correctable error is detected. The counter stops counting after reaching 0xFF. Cleared by read. Uncorrectable Error Count (uncorr_err_cnt). This counter is incremented 0x0 every time an uncorrectable error is detected ...
Page 133
... Receiver Timer Interrupt (RXT0). Set when the timer expires. LCAPD Exit Interrupt (LCAPD). Set when the Intel 0b Chipset takes the MAC out of LCAPD state. 0b MDIO Access Complete (MDAC). Set when the MDIO access completes. ...
Page 134
... For example, if the interval is programmed to 500d, the network controller guarantees the CPU is not interrupted by the network controller for 128 ms from the last interrupt. 127 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Small Receive Packet Detected (SRPD). Indicates that a packet size < ...
Page 135
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Inversely, inter-interrupt interval value can be calculated as: inter-interrupt interval = (256 x 10 The optimal performance setting for this register is very system and configuration specific. An initial suggested range for the interval value is 65--5580 (28B - 15CC). ...
Page 136
... RXO. Sets mask for receiver overrun. Set on receive data FIFO overrun. 0b RXT0. Sets mask for receiver timer interrupt. LCAPD. Sets mask for LCAPD interrupt. LCAPD mask is set after reset to 0b enable LCAPD interrupt (driven by Intel 0b MDAC. Sets mask for MDIO access complete interrupt. 00b Reserved. ...
Page 137
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.2.5 Interrupt Mask Clear Register - IMC (0x000D8; WO) Bit Type 11: 31:23 RO Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only when the mask bit and the cause bit is a 1b. The status of the ...
Page 138
... RW 13: 131 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset IAM_VALUE. When the CTRL_EXT.IAME bit is set and the 0x0 ICR.INT_ASSERTED=1, an ICR read or write has the side effect of writing the contents of this register to the IMC register. Reset Reserved ...
Page 139
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Bit Type 15 RW 17:16 RW 21: 30: Reset Description Broadcast Accept Mode (BAM Ignore broadcast (unless it matches through exact or imperfect 0b filters Accept broadcast packets. Receive Buffer Size (BSIZE). RCTL.BSEX – zero: 00b = 2048 bytes. ...
Page 140
... The SECRC bit controls whether hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations. The stripped CRC is not DMA'd to host memory and is not included in the length reported in the descriptor. 133 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Free Buffer Threshold 1/2 1/4 ...
Page 141
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.3.2 Receive Control Register 1 - RCTL1 (0x00104; RW) Bit Type 7:0 RO 9:8 RW 11:10 RW 15:12 RO 17:16 RW 24: 30: Reset Reserved. This bit represents a hardware reset of the receive-related portion of the device in previous controllers, but is no longer applicable. ...
Page 142
... When early receive is used in parallel to the packet split feature, the minimum value of the ERT register should be bigger than the header size to enable the actual packet split. 135 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset Receive Threshold Value (RxThreshold). This threshold is in units of eight 0x0 bytes ...
Page 143
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.3.4 Packet Split Receive Control Register - PSRCTL (0x02170) Bit Type 6 13:8 RW 15:14 RO 21:16 RW 23:22 RO 29:24 RW 31:30 RO Note: If software sets a buffer size to zero, all buffers following that one must be set to zero as well ...
Page 144
... RW X This register contains the upper 32 bits of the 64-bit descriptor base address. 137 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Reset 0x0 Reserved. Must be written with 0. Receive Threshold High (RTH). FIFO high water mark for flow control 0x0 transmission ...
Page 145
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.3.9 Receive Descriptor Length Queue- RDLEN (0x02808; RW) Bits Type Reset 6:0 RO 0x0 19:7 RW 0x0 31:20 RO 0x0 This register sets the number of bytes allocated for descriptors in the circular descriptor buffer. It must be 128-byte aligned. ...
Page 146
... PCI configuration space CLS field) must not represent greater than 31 descriptors. Note: When (WTHRESH = 0b) or (WTHRESH = 1b and GRAN = 1b) only descriptors with the RS bit set is written back. 139 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Prefetch Threshold (PTHRESH). Reserved. Host Threshold (HTHRESH). Reserved. ...
Page 147
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY PTHRESH is used to control when a prefetch of descriptors is considered. This threshold refers to the number of valid, unprocessed receive descriptors the chip has in its on- chip buffer. If this number drops below PTHRESH, the algorithm considers pre-fetching descriptors from host memory ...
Page 148
... RSS hash. Only one of the two options is reported in the Rx descriptor. The RXCSUM.PCSD affect is shown in the following table: 141 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description SIZE. If the interrupt is enabled any receive packet of size <= SIZE asserts an interrupt. SIZE is specified in bytes and includes the headers and the CRC. It does not include the VLAN header in size calculation stripped ...
Page 149
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY RXCSUM.PCSD Legacy Rx descriptor (RCTL.DTYP = 00b) Extended or header split Rx descriptor (RCTL.DTYP = 01b) PCSS IPPCSE: The PCSS and the IPPCSE control the packet checksum calculation. As previously noted, the packet checksum shares the same location as the RSS field. The packet checksum is reported in the receive descriptor when the RXCSUM ...
Page 150
... Multicast offset in the CTRL equals 00b. The complete multicast offset options are: 143 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description iSCSI Disable (ISCSI_DIS). Disable the iSCSI filtering for header split functionality ...
Page 151
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Multicast Offset 00b 01b 10b 11b MO1:0] Figure 19. Multicast Table Array Algorithm 10.2.1.3.20 Receive Address Low - RAL (0x05400 + 8*n (n=0…6); RW) While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6. ...
Page 152
... RW 0b 145 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Receive Address High (RAH). The upper 16 bits of the 48-bit Ethernet address n (n=0, 1…6). RAH 0 is loaded from word 2 in the NVM. Address Select (ASEL). Selects how the address used. Decoded as follows: 00b = Destination address (must be set to this in normal mode) ...
Page 153
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.3.24 Shared Receive Address High 3 - SHRAH[3] (0x05454; RW) Bits Type Reset 15 17:16 RO 00b 29:19 RO 0x0 10.2.1.3.25 Multiple Receive Queues Command register - MRQC (0x05818; RW) Bits Type Reset 1:0 RW 0x00b 15:2 0x0 21:16 ...
Page 154
... RW 0x0 31:24 RW 0x0 147 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface 31:24 23:16 Tag 4*n+2 Tag 4*n+1 Description CPU INDX 0. CPU index for Tag 4*n (n=0,1,…31). Reserved. QUE INDX 0. Queue Index for Tag 4*n (n=0,1,…31). ...
Page 155
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.4 Transmit Register Descriptions 10.2.1.4.1 Transmit Control Register - TCTL (0x00400; RW) Bits Type Reset 11:4 RW 0x0F 21:12 RW 0x3F 22 RW 27:25 RW 0x0 28 1b 30:29 RW 01b Two fields deserve special mention: CT and COLD. Software might choose to abort packet transmission in less than the Ethernet mandated 16 collisions ...
Page 156
... In summary, the recommended TIPG value to achieve 802.3 compliant minimum transmit IPG values in full and half duplex is 0x00702008. 149 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description IPG Transmit Time (IPGT). Specifies the IPG length for back-to-back transmissions equal to [(IPGT+ bit time ...
Page 157
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.4.3 Adaptive IFS Throttle - AIT (0x00458; RW) Bits Type Reset 15:0 RW 0x0000 31:16 RO 0x0000 Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function, and thus can be used to delay the transmission of back-to-back packets on the wire ...
Page 158
... ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set). 151 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Reserved. Ignore on write. Reads back as 0b. Descriptor Length (LEN). ...
Page 159
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY This feature operates by initiating a countdown timer upon successfully transmitting the buffer subsequent transmit delayed-interrupt is scheduled BEFORE the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated ...
Page 160
... GRAN = 1 (descriptor granularity): PTHRESH = 0..31 WTHRESH = 0..31 HTHRESH = 0..31 GRAN = 0 (cacheline granularity): PTHRESH = 0..3 (for 16 descriptors cacheline - 256 bytes) 153 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Prefetch Threshold (PTHRESH). Reserved. Host Threshold (HTHRESH). Reserved. Write-Back Threshold (WTHRESH). ...
Page 161
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY WTHRESH = 0..3 HTHRESH = 0..4 Note: For any WTHRESH value other than zero - The packet and absolute timers must get a non zero value for the WTHRESH feature to take affect. Note: Since the default value for write-back threshold is zero, descriptors are normally written back as soon as they are processed ...
Page 162
... If there is NO VAUX, then the PME Status bits should be cleared by: — LAN_RST# or PCI reset — PCI reset de-assertion — Explicit software clear 155 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Advance Power Management Enable (APME APM Wakeup is enabled APM Wakeup is disabled. ...
Page 163
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.5.2 Wake Up Filter Control Register - WUFC (0x05808; RW) Bits Type Reset 14:8 RO 0x0 31:2 RO 0x0 This register is used to enable each of the pre-defined and flexible filters for wake up support. A value of 1b means the filter is turned on, and a value of 0b means the filter is turned off ...
Page 164
... The IP6AT has the following format: Bits Type Reset 31 157 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description FLX4. Flexible Filter 4 Match. FLX5. Flexible Filter 5 Match. Reserved. Description Reserved. V41. IPv4 Address 1 Valid. ...
Page 165
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY 10.2.1.5.7 Flexible Filter Length Table - FFLT (0x05F00 + 8*n (n=0…5); RW) There are six flexible filters Lengths. The flexible filter length table stores the minimum packet lengths required to pass each of the flexible filters. Any packets that are shorter than the programmed length does not pass that filter ...
Page 166
... Flexible Filter Enable bits of the Wake Up Filter Control register (WUFC.FLXn). 159 ® 82578 GbE PHY—Intel 5 Series Express Chipset MAC Programming Interface Description Value 1. Value of filter 1 byte n (n=0, 1… 127). Value 2. Value of filter 2 byte n (n=0, 1… 127). ...
Page 167
... Intel 5 Series Express Chipset MAC Programming Interface—82578 GbE PHY Note: This page intentionally left blank. 160 ...
Page 168
... Recommended operation conditions require accuracy of power supply of +/-5% relative to the nominal voltage. 3. Maximum ratings are referenced to ground (VSS). 161 82578 GbE PHY—Electrical and Timing Specifications Parameter Case Temperature Under Bias Storage Temperature Range 3.3 Vdc I/O Voltage 2.5 Vdc I/O Voltage 1 ...
Page 169
... Electrical and Timing Specifications—82578 GbE PHY 11.2.2 Recommended Operating Conditions Symbol Ta 1. For normal device operation, adhere to the limits in this table. Sustained operations of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated Vdc and Vac limits is not guaranteed if conditions exceed recommended operating conditions ...
Page 170
... Maximum voltage ripple (peak to peak) @ Ripple Overshoot Maximum overshoot allowed 11.3.1.2 1.8 Vdc Rail Title Operational Range Voltage range for normal operating conditions Maximum voltage ripple (peak to peak) @ Ripple 163 82578 GbE PHY—Electrical and Timing Specifications Description Min 0.1 N/A 90 N/A 20 MHz BW N/A Description Min 1 ...
Page 171
... Electrical and Timing Specifications—82578 GbE PHY 11.3.1.3 1.2 Vdc Rail Title Rise Time Monotonicity Ramp rate at any given time between 10% Slope Operational Range Maximum voltage ripple (peak to peak) @ Ripple Overshoot Decoupling Capacitance Capacitance ESR 11.3.1.4 1.2 Vdc PNP Regulator Power Delivery Schematic ...
Page 172
... All the 3.3 Vdc I/Os are open-drain types. Parameter Conditions VIL VIH VOL VOH Ipullup Ileakage Ci 165 82578 GbE PHY—Electrical and Timing Specifications Electrical Qty Characteristics • Minimum HFE (Vdc Gain Vce = 2.5 Vdc I= 0.35A C • Rja<60 CW Parameter Min 2 ...
Page 173
... Electrical and Timing Specifications—82578 GbE PHY Signal Name 1 CLK_REQ_N SMB_CLK SMB_DATA 1. Ileakage applies only when the PHY is powered on. 11.4.2 2.5 Vdc/IO Parameter Conditions VIL VIH I = VOL VCC = Min VOH VCC = Min Ipullup Ileakage Bus Description Size 1 Open drain I/O 1 Open drain I(H)/O ...
Page 174
... LED[2:0] JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TCK 11.4.3 Input Buffer Only Parameter Conditions VIL VIH Ipullup Ileakage Ci Signal Name Internal Power On Reset/ LAN_DISABLE_N TEST_EN PE_RST_N 167 82578 GbE PHY—Electrical and Timing Specifications Bus Description Size I/O, PU Minimum Typical -0 3.3 ...
Page 175
... Electrical and Timing Specifications—82578 GbE PHY 11.4.4 SMBus AC I/O Refer to the System Management Bus (SMBus) Specification Version 2.0. 11.4.5 PCIe DC/AC Specifications 11.4.5.1 PCIe Specifications (Transmitter) Symbol Parameter UI Unit interval Differential peak-to-peak Tx voltage V tx-diff-pp swing Transmitter eye including all jitter ...
Page 176
... RL Rx differential return loss rx-diff return loss rx- impedance rx- differential Vdc impedance rx-diff- Vac CM voltage rx-cm-ac-p 169 82578 GbE PHY—Electrical and Timing Specifications 600 mV 400 -400 mV -600 mV 0 100 175 625 Time (pS) Note: Not To Scale 1.25 GT/s Min Max 799.92 800.08 ...
Page 177
... Electrical and Timing Specifications—82578 GbE PHY Symbol Parameter Z rx-high-imp-dc- DC input CM impedance for V>0 pos Z rx-high-imp-dc- DC input CM impedance for V<0 neg V Electrical idle detect threshold rx-idle-det-diffp-p T rx-idle-det-diff- Unexpected electrical idle detect entertime Note: Figure 21 is intented to show the difference between the PCIe 1.0 and PCIe-based receiver sensitivity templates ...
Page 178
... MHz through 500 MHz 1.0 MHz through 270 MHz CM to CMR 270.1 MHz through 300 MHz 300.1 MHz through 500 MHz 171 82578 GbE PHY—Electrical and Timing Specifications Condition 1500 Vrms (min) 2250 Vdc (min) 400 H (min) 350 H (min (max) 0 ...
Page 179
... Df/f ±30 [ppm ] max [pF] load C 6 [pF] max o D 200 [ W] max L Df/f ±5 ppm per year ±5 ppm per year max o Parallel 500 [M ] min ). Refer to the crystal design guidelines in the Intel L Conditions @25 [°C] @25 [°C] @25 [MHz] @ 100 Vdc ® 172 ...
Page 180
... TL_XTAL_IN TJ_XTAL_IN 1. Conditioning circuit required to limit the voltage swing of VIH/VIL to 1.2 Vdc. 2. Broadband peak-to-peak = 200 pS, Broadband rms = 3 pS, 12 KHz to 20 MHz rms = 1 ps Figure 22. XTAL Timing Diagram 173 82578 GbE PHY—Electrical and Timing Specifications Symbol/Parameter Conditions f @25 [°C] o Vp-p f/f ...
Page 181
... Electrical and Timing Specifications—82578 GbE PHY Note: Peak-to-peak voltage presented at the XTAL1 input cannot exceed 1.8 Vdc. Figure 23. Clock Oscillator Schematic 174 ...
Page 182
... Schematic and Board Layout Checklists The 82578 Design and Board Layout Checklists can be found at www.intel.com. 175 82578 GbE PHY—Schematic and Board Layout Checklists ...
Page 183
... Schematic and Board Layout Checklists—82578 GbE PHY Note: This page intentionally left blank. 176 ...
Page 184
... Reference Schematics The 82578 reference schematics can be found at www.intel.com. 177 82578 GbE PHY—Reference Schematics ...
Page 185
... Reference Schematics—82578 GbE PHY Note: This page intentionally left blank. 178 ...
Page 186
... Models Contact your Intel Representative for access to the 82578 IBIS model. 179 82578 GbE PHY—Models ...
Page 187
... Models—82578 GbE PHY Note: This page intentionally left blank. 180 ...