WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet - Page 160

• Manufacturer Part Number: WG82578DM S LGY6
• Manufacturer: Intel

Specifications of WG82578DM S LGY6

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.2.1.4.10 Transmit Descriptor Control - TXDCTL (0x03828; RW)
Note:
Note:
Note:
153
This register was not fully validated. Software should set it to 0x0000 during nominal
operation.
This register controls the fetching and write back of transmit descriptors. The three
threshold values are used to determine when descriptors is read from and written to
host memory. The values might be in units of cache lines or descriptors (each
descriptor is 16 bytes) based on the GRAN flag.
When GRAN = one all descriptors is written back (even if not requested).
PTHRESH is used to control when a prefetch of descriptors is considered. This threshold
refers to the number of valid, unprocessed transmit descriptors the chip has in its on-
chip buffer. If this number drops below PTHRESH, the algorithm considers pre-fetching
descriptors from host memory. This fetch does not happen however, unless there are at
least HTHRESH valid descriptors in host memory to fetch.
HTHRESH should be given a non-zero value each time PTHRESH is used.
WTHRESH controls the write back of processed transmit descriptors. This threshold
refers to the number of transmit descriptors in the on-chip buffer which are ready to be
written back to host memory. In the absence of external events (explicit flushes), the
write back occurs only after at least WTHRESH descriptors are available for write back.
Possible values:
GRAN = 1 (descriptor granularity):
PTHRESH = 0..31
WTHRESH = 0..31
HTHRESH = 0..31
GRAN = 0 (cacheline granularity):
PTHRESH = 0..3 (for 16 descriptors cacheline - 256 bytes)
5:0
7:6
13:8
15:14
21:16
23:22
24
31:25
Bits
RW
RO
RW
RO
RW
RO
RW
RW
Type
0x00
0x00
0x00
0x00
0x00
0x00
0x0
0x0
Reset
82578 GbE PHY—Intel
Prefetch Threshold (PTHRESH).
Reserved.
Host Threshold (HTHRESH).
Reserved.
Write-Back Threshold (WTHRESH).
Reserved.
Granularity (GRAN). Units for the thresholds in this register.
0b = Cache lines.
1b = Descriptors.
Transmit descriptor Low Threshold (LWTHRESH).
Interrupt asserted when the number of descriptors pending service in the transmit
descriptor queue (processing distance from the TDT) drops below this threshold.
®
5 Series Express Chipset MAC Programming Interface
Description