WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet - Page 115

• Manufacturer Part Number: WG82578DM S LGY6
• Manufacturer: Intel

Specifications of WG82578DM S LGY6

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
10.2
Note:
Note:
®
5 Series Express Chipset MAC Programming Interface—82578 GbE PHY
The following exceptions use network ordering:
• All ETherType fields
The normal notation as it appears in text books, etc. is to use network ordering. For
example, the following MAC address: 00-A0-C9-00-00-00. The order on the network is
00, then A0, then C9, etc. However, the host ordering presentation would be:
Register Conventions
All registers in the MAC are defined to be 32 bits, so write cycles should be accessed as
32 bit double-words, There are some exceptions to this rule:
Reserved bit positions: Some registers contain certain bits that are marked as
reserved. These bits should never be set to a value of 1b by software. Reads from
registers containing reserved bits might return indeterminate values in the reserved bit
positions unless read values are explicitly stated. When read, these reserved bits
should be ignored by software.
Reserved and/or undefined addresses: any register address not explicitly declared in
this document should be considered to be reserved, and should not be written to.
Writing to reserved or undefined register addresses might cause indeterminate
behavior. Reads from reserved or undefined configuration register addresses might
return indeterminate values unless read values are explicitly stated for specific
addresses. Reserved fields within defined registers are defined as Read-Only (RO).
When writing to these registers, the RO fields should be set to their initial value.
Reading from reserved fields might return indeterminate values.
Initial values: most registers define the initial hardware values prior to being
programmed. In some cases, hardware initial values are undefined and are listed as
such via the text undefined, unknown, or X. Some of these configuration values might
need to be set via NVM configuration or via software in order for proper operation to
occur. Note that this need is dependent on the function of the bit. Other registers might
cite a hardware default that is overridden by a higher-precedence operation.
Operations that might supersede hardware defaults might also include a valid NVM
load, completion of a hardware operation (such as hardware auto-negotiation), or
writing of a different register whose value is then reflected in another bit.
For registers that should be accessed as 32-bit double words, partial writes (less than a
32-bit double word) does not take effect (the write is ignored). Partial reads return all
32 bits of data regardless of the byte enables.
Partial reads to read-on-clear registers (such as ICR) can have unexpected results since
all 32 bits are actually read regardless of the byte enables. Partial reads should not be
done.
All statistics registers are implemented as 32-bit registers. Though some logical
statistics registers represent counters in excess of 32 bits in width, registers must be
accessed using 32-bit operations (like independent access to each 32-bit field).
• Register pairs where two 32-bit registers make up a larger logical size
Dword address (N)
Dword address (N + 4)
Byte 3
00
...
Byte 2
C9
...
Byte 1
A0
00
Byte 0
00
00
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