WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet - Page 158

• Manufacturer Part Number: WG82578DM S LGY6
• Manufacturer: Intel

Specifications of WG82578DM S LGY6

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.2.1.4.6
Note:
10.2.1.4.7
10.2.1.4.8
Note:
10.2.1.4.9
151
Transmit Descriptor Length - TDLEN (0x03808 ; RW)
This register contains the descriptor length and must be 128-byte aligned.
The descriptor ring must be equal to or larger than eight descriptors.
Transmit Descriptor Head - TDH (0x03810; RW)
This register contains the head pointer for the transmit descriptor ring. It points to a
16-byte datum. Hardware controls this pointer. The only time that software should
write to this register is after a reset (hardware reset or CTRL.SWRST) and before
enabling the transmit function (TCTL.EN). If software were to write to this register
while the transmit function was enabled, the on-chip descriptor buffers might be
invalidated and hardware could be become confused.
Transmit Descriptor Tail - TDT (0x03818; RW)
This register contains the tail pointer for the transmit descriptor ring. It points to a 16-
byte datum. Software writes the tail pointer to add more descriptors to the transmit
ready queue. Hardware attempts to transmit all packets referenced by descriptors
between head and tail.
Transmit Interrupt Delay Value - TIDV (0x03820; RW)
This register is used to delay interrupt notification for transmit operations by coalescing
interrupts for multiple transmitted buffers. Delaying interrupt notification helps
maximize the amount of transmit buffers reclaimed by a single interrupt. This feature
ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is
requested (RS set) and (b) the use of the timer function is requested (IDE is set).
6:0
19:7
31:20
15:0
31:16
15:0
31:16
15:0
30:16
31
Bits
Bits
Bits
Bits
RO
RW
RO
RW/V
RO
RW
RO
RW
RO
WO
Type
Type
Type
Type
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0b
Reset
Reset
Reset
Reset
82578 GbE PHY—Intel
Reserved. Ignore on write. Reads back as 0b.
Descriptor Length (LEN).
Reserved. Reads as 0b. Should be written to 0b.
Transmit Descriptor Head (TDH).
Reserved. Should be written with 0b.
Transmit Descriptor Tail (TDT).
Reserved. Reads as 0b. Should be written to 0 for future compatibility.
Interrupt Delay Value (IDV). Counts in units of 1.024 ms. A value of zero is not
allowed.
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
Flush Partial Descriptor Block (FPD). when set to 1b; ignored otherwise. Reads 0b.
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description
Description