WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet - Page 119

• Manufacturer Part Number: WG82578DM S LGY6
• Manufacturer: Intel

Specifications of WG82578DM S LGY6

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
10.2.1.1
10.2.1.1.1
®
5 Series Express Chipset MAC Programming Interface—82578 GbE PHY
General Register Descriptions
Device Control Register - CTRL (0x00000; RW)
0
1
2
5:3
6
7
9:8
10
11
12
13
14
15
18:16
19
20
24:21
25
26
27
Bit
RW/SN
RO
RW
RO
RO
RO
RW
RO
RW/SN
RW
RO
RW/SN
RO
RW
RW
RO
RW
RW/V
RW
Type
1b
0b
0b
000b
1b
0b
10b
0b
0b
0b
0b
0b
0b
0b
1b
0b
0b
0b
0b0
0x0
Reset
Full Duplex (FD).
0b = Half duplex.
1b = Full duplex.
Controls the MAC duplex setting when explicitly set by software. Loaded
from the NVM word 0x13.
Reserved. Write as 0b for future compatibility
Master Disable. When set, the MAC blocks new master requests on the
PCI device. Once no master requests are pending by this function, the
Master Enable Status bit is cleared.
Reserved. Write as 0b for future compatibility.
Reserved.
Reserved.
Speed selection (SPEED). These bits might determine the speed
configuration and are written by software after reading the PHY
configuration through the MDIO interface. These signals are ignored when
auto-speed detection is enabled.
0)b = 10 Mb/s.
0)b = 100 Mb/s.
10b = 1000 Mb/s.
11b = Not used.
Reserved. Write as 0b for future compatibility.
Force Speed (FRCSPD). This bit is set when software needs to manually
configure the MAC speed settings according to the Speed bits (bits 9:8).
When using the 82578, note that it must resolve to the same speed
configuration or software must manually set it to the same speed as the
MAC. The value is loaded from word 0x13 in the NVM.
Note that this bit is superseded by the CTRL_EXT.SPD_BYPS bit, which
has a similar function.
Force Duplex (FRCDPLX). When set to 1b, software might override the
duplex indication from the 82578 that is indicated in the FDX to the MAC.
Otherwise, the duplex setting is sampled from the 82578 FDX indication
into the MAC on the asserting edge of the PHY link signal. When asserted,
the CTRL.FD bit sets duplex.
Reserved.
Reserved.
Reserved. Reads as 0.
Reserved.
Memory Error Handling Enable (MEHE). When set to 1b, the Intel® 5
Series Express Chipset reaction to correctable and uncorrectable memory
errors detection are activated.
Reserved.
Reserved.
Reserved.
Host Software Reset (SWRST). This bit performs a reset to the PCI data
path and the relevant shared logic. Writing 1b initiates the reset. This bit
is self-clearing.
Receive Flow Control Enable (RFCE). Indicates that the MAC responds to
receiving flow control packets. If auto-negotiation is enabled, this bit is
set to the negotiated duplex value.
Must be set to 0b.
Description
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