WG82578DM S LGY6 Intel, WG82578DM S LGY6 Datasheet - Page 85

• Manufacturer Part Number: WG82578DM S LGY6
• Manufacturer: Intel

Specifications of WG82578DM S LGY6

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmer’s Visible State—82578 GbE PHY
Note:
Note:
Table 66.
All wake up registers (page 800-801 except CTRL and IPAV) are not cleared with PHY
reset is asserted. It is only cleared when internal power on reset is de-asserted or when
cleared by the software device driver.
Access to page 800/801 should be done only in 10 Mb/s and 100 Mb/s.
PMCF controls the usage of MAC control frames (including flow control). A MAC control
frame in this context must be addressed to the flow control multicast address
0x0100_00C2_8001 and match the type field (0x8808). If PMCF=1b, then frames
meeting this criteria participate in wake up filtering.
Wake Up Control – WUC PHY Address 01, Page 800, Register 1
RW/SN
RW/V
RWC
RO
RW/SN
RW/SN
RO
Attribute
0
1
2
3
4
5
15:6
Bit(s)
0b
0b
0b
0b
0b
0b
0x00
Initial Value
Advance Power Management Enable (APME)
If set to 1b, APM wake up is enabled.
PME_En
If set to 1b, ACPI wake up is enabled.
PME_Status
This bit is set when the 82578 receives a wake up event.
Reserved
Link Status Change Wake Enable (LSCWE)
Enables wake on link status change as part of APM wake capabilities.
Link Status Change Wake Override (LSCWO)
If set to 1b, wake on link status change does not depend on the LNKC bit
in the WUFC register. Instead, it is determined by the APM settings in the
WUC register.
Reserved
Description
78