PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 105

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PEB20534H-10V2.1

Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
Datasheets

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until the bus cycle is complete, then drive it low again. By inserting predefined waitstates
the first LRDY sample point can be shifted to a time, where the peripheral has safely
controlled the LRDY line (e.g. after 2 waitstates, see
Figure 28
Data Sheet
(write cycle)
(read cycle)
LRD, LWR
LD[15..0]
LD[15..0]
Notes:
- MCTC wait state configuration is assumed to one cycle in this figure
- LRDY is evaluated the first time with the clock cycle following the MCTC related wait states
- Transaction is terminated one clock cycle after detecting LRDY active
- LRDY is evaluated only if LRDY-control is enabled
LCLKO
LRDY
LRDY Timing
2 cycles fix
105
MCTC
first LRDY
evaluation
Figure 27
(LRDY active)
last LRDY
evaluation
Multi Function Port (MFP)
65
and
transaction
termination
66
Figure
PEB 20534
PEF 20534
28).
2000-05-30

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