PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 144

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PEB20534H-10V2.1

Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
Datasheets

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7.4.1.4
The BRG is fed with an externally generated clock via pin RxCLK. Depending on the
value of bit ’SSEL’ in register CCR0 the BRG delivers either a reference clock for the
DPLL which is 16 times of the resulting DPLL output frequency or delivers directly the
receive and transmit clock (clock mode 3b). In the first case (clock mode 3a) the DPLL
output clock is used as receive and transmit clock.
Figure 45
Data Sheet
Clock Mode 3 (3a/3b)
clock mode 3a
clock mode 3b
Clock Mode 3a/3b Configuration
Ctrl.
Ctrl.
DPLL
BRG
BRG
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
Serial Communication Controller (SCC) Cores
144
(tx clock monitor output)
(tx clock monitor output)
clock supply
clock supply
1
1
PEB 20534
PEF 20534
2000-05-30

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