PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 267

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 61
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
CHiFTDA
30
14
CHiFTDA:
Channel i First (Current) Transmit Descriptor Address Register
(i=3...0)
i = 3...0
The DMA controller writes the first/current address of the channel
specific transmit descriptor chain to these registers, i.e. the address of
the transmit descriptor, the DMA transmit channel i is currently working
on.
These registers are only valid, if the DMA controller is operating in Last
Descriptor Address Mode (bit CMODE set to ’1’ in register GMODE).
29
13
28
12
read/write
0000 0000
Channel 0
00B0
written by DSCC4
evaluated by CPU
27
11
H
26
10
H
CHiFTDA(15:2)
Channel 1
00B4
25
9
CHiFTDA(31:16)
H
24
267
8
23
7
Channel 2
00B8
22
6
H
Detailed Register Description
21
5
20
4
Channel 3
00BC
19
(TX Channel 3...0)
3
H
18
2
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0