PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 70

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

The following figure provides an example, how a transmit descriptor and its associated
data buffer is located in the memory as a result of a memory dump.
Figure 14
Note: Although transmit descriptors consist of only 4 DWORDs it might be useful to
Data Sheet
DSCC4 register CH0BTDA:
Base Transmit Descriptor Address Channel 0
31
31
Next Transmit Descriptor Ptr.=0x10001014
1
04
08
00
Transmit Data Pointer= 0x20000020
0
allocate 5 DWORD structures to achieve compatibility between transmit and
receive descriptors. In this case only small CPU performed manipulations are
necessary to convert a completed receive descriptor into a transmit descriptor re-
chained to a transmit descriptor list. This is typical e.g. for frame relay or bridging
applications where received data might be sent out again on another DSCC4 port.
0
CH0BTDA = 0x10001000
(dummy) 0x00000000
written by
CPU
written by
DSCC4
0x009
03
07
00
0x40000000
Transmit Descriptor Memory Example
02
06
00
01
05
09
0
0
70
FE Hold HI
DMA Controller and Central FIFOs
Host Memory Dump:
Value:
31
0x80090000
0x10001014
0x20000020
0x40000000
0x00000000
0x04030201
0x08070605
0x00000009
0
PEB 20534
PEF 20534
Address:
0x10001000
0x10001004
0x10001008
0x1000100C
0x10001010
0x10001014
0x20000020
0x20000024
0x20000028
0x20000030
2000-05-30