PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 276

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
XRES
HUNT
RFRD
Transmitter Reset Command
Self-clearing command bit:
XRES=’1’
Enter Hunt State Command
Self-clearing command bit:
HUNT=’1’
Receive FIFO Read Enable Command
Self-clearing command bit:
RFRD=’1’
The SCC transmit FIFO is cleared and the transmitter
protocol engines are reset to their initial state.
The SCC transmit FIFO requests new transmit data from
the central TFIFO immediately after transmitter reset
procedure.
A transmitter reset command is recommended after all
changes in protocol mode configurations (switching
between the protocol engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
This command forces the receiver to enter its ’HUNT’
state immediately. Thus synchronization is ’lost’ and the
receiver starts searching for new SYNC characters.
This command forces insertion of a ’block end’ indication
in the SCC receive FIFO. If the receive FIFO is not empty
(bit ’RFNE’ set in register STAR) and data was not
transferred to the central RFIFO because neither the
receive threshold is exceeded nor a block end indication
is stored, this command forces data transfer to the central
RFIFO.
Note: This command always generates a ’block-end’
indication. If the receive FIFO was empty, the DMA
Controller will finish the current receive descriptor
with receive byte number zero and frame-end/
block-end indication bit set.
276
Detailed Register Description
(async/bisync mode)
(bisync mode)
PEB 20534
PEF 20534
(all modes)
2000-05-30