PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 399

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

12
12.1
In the DSCC4 a Test Access Port (TAP) controller is implemented. The essential part of
the TAP is a finite state machine (16 states) controlling the different operational modes
of the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE 1149.1.
controller.
Figure 82
If no boundary scan operation is planned TRST has to be connected with V
TDI do not need to be connected since pull-up transistors ensure high input levels in this
case. Nevertheless it would be a good practice to put the unused inputs to defined levels.
In this case, if the JTAG is not used:
TMS = TCK = ’1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i.e. TRST is connected to V
unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock
Data Sheet
TCK
TRST
TMS
TDI
TDO
Test Configuration
JTAG Boundary Scan Interface
Block Diagram of Test Access Port and Boundary Scan Unit
CLOCK
Reset
Test
Control
Data in
Enable
Data out
Test Access Port (TAP)
- Finite State Machine
- Instruction Register (3 bit)
- Test Signal Generator
Clock Generation
TAP Controller
CLOCK
399
Figure 82
gives an overview about the TAP
ID Data out
Control
Bus
SS Data
out
6
Test Configuration
DD
or it remains
PEB 20534
2
1
n
PEF 20534
SS
Pins
.
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.
.
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. TMS and
2000-05-30