C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 13

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

1. System Overview
C8051T600/1/2/3/4/5/6 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted
features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering num-
bers.
With on-chip power-on reset, V
devices are truly stand-alone, system-on-a-chip solutions. User software has complete control of all
peripherals and may individually shut down any or all peripherals for power savings.
Code written for the C8051T600/1/2/3/4/5/6 family of processors will run on the C8051F300 Mixed-Signal
ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring special
emulator circuitry. The C8051T600/1/2/3/4/5/6 processors include Silicon Laboratories’ 2-Wire C2 Debug
and Programming interface, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection
of memory, viewing and modification of special function registers, setting breakpoints, single stepping, and
run and halt commands. All analog and digital peripherals are fully functional while debugging using C2.
The two C2 interface pins can be shared with user functions, allowing in-system debugging without occu-
pying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant
of input signals up to 5 V. See Table 2.1 for ordering information. Block diagrams of the devices in the
C8051T600/1/2/3/4/5/6 family are shown in Figure 1.1, Figure 1.2, and Figure 1.3.
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High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
C8051F300 ISP Flash device is available for quick in-system code development
10-bit 500 ksps Single-ended ADC with analog multiplexer and integrated temperature sensor
Precision calibrated 24.5 MHz internal oscillator
8 k, 4 k, 2 k or 1.5 kB of on-chip Byte-Programmable EPROM—(512 bytes are reserved on 8k version)
256 or 128 bytes of on-chip RAM
SMBus/I
Three general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer function
On-chip Power-On Reset and Supply Monitor
On-chip Voltage Comparator
8 or 6 Port I/O
2
C, and ART serial interfaces implemented in hardware
DD
monitor, watchdog timer, and clock oscillator, the C8051T600/1/2/3/4/5/6
Rev. 1.2
C8051T600/1/2/3/4/5/6
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