C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 134

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

C8051T600/1/2/3/4/5/6
23.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK or ignore the received slave address with a NACK.
If the received slave address is ignored by software (by NACKing the address), slave interrupts will be
inhibited until the next START is detected. If the received slave address is acknowledged, zero or more
data bytes are transmitted. If the received slave address is acknowledged, data should be written to
SMB0DAT to be transmitted. The interface enters slave transmitter mode and transmits one or more bytes
of data. After each byte is transmitted, the master sends an acknowledge bit. If the acknowledge bit is an
ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT
should not be written to before SI is cleared (an error condition may be generated if SMB0DAT is written
following a received NACK while in slave transmitter mode). The interface exits slave transmitter mode
after receiving a STOP. Note that the interface will switch to slave receiver mode if SMB0DAT is not written
following a Slave Transmitter interrupt. Figure 23.8 shows a typical slave read sequence. Two transmitted
data bytes are shown, though any number of bytes may be transmitted. Notice that all of the “data byte
transferred” interrupts occur after the ACK cycle in this mode.
23.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. Table 23.4 describes the
typical actions taken by firmware on each condition. In the table, STATUS VECTOR refers to the four upper
bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typical
responses; application-specific procedures are allowed as long as they conform to the SMBus specifica-
tion. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
134
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.8. Typical Slave Read Sequence
R
A
Data Byte
Rev. 1.2
Interrupt Locations
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
P