C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 59

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

13. Comparator0
C8051T600/1/2/3/4/5/6 devices include an on-chip programmable voltage comparator, Comparator0,
shown in Figure 13.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “22.4. Port I/O Initialization” on page 114). Comparator0 may also be used as a reset source (see
Section “19.5. Comparator0 Reset” on page 94).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“13.1. Comparator Multiplexer” on page 63.
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “22.3. Priority Crossbar Decoder” on
page 111 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0EN
CP0FIF
CP0MD1
CP0MD0
Figure 13.1. Comparator0 Functional Block Diagram
Comparator
Input Mux
CP0 +
CP0 -
+
-
VDD
GND
Rev. 1.2
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
C8051T600/1/2/3/4/5/6
D
SET
CLR
Q
Q
Interrupt Flag
Rising-edge
CP0
Crossbar
Interrupt
Logic
Interrupt Flag
Falling-edge
CP0
CP0A
CP0
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