AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 144

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

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Transmission Modes
AT89LP51RB2/RC2/IC2 Preliminary
Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
4. When the address packet has been transmitted, the SI flag in SSCON is set, and SSCS
5. The application software should now examine the value of SSCS, to make sure that the
6. When the data packet has been transmitted, the SI flag in SSCON is set, and SSCS is
7. The application software should now examine the value of SSCS, to make sure that the
• When the TWI has finished an operation and expects application response, the SI flag is set.
• When the SI flag is set, the user must update all TWI registers with the value relevant for the
• After all TWI Register updates and other pending application software tasks have been
The SCL line is pulled low until SI is cleared.
next TWI bus cycle. As an example, SSDAT must be loaded with the value to be transmitted
in the next bus cycle.
completed, SSCON is written. When writing SSCON, the SI bit should be cleared. The TWI
will then commence executing whatever operation was specified by the SSCON setting.
is updated with a status code indicating that the address packet has successfully been
sent. The status code will also reflect whether a slave acknowledged the packet or not.
address packet was successfully transmitted, and that the value of the ACK bit was as
expected. If SSCS indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must load a data packet into SSDAT. Subsequently, a specific value
must be written to SSCON, instructing the TWI hardware to transmit the data packet
present in SSDAT. Which value to write is described later on. However, it is important
that the SI bit is cleared in the value written. The TWI will not start any operation as long
as the SI bit in SSCON is set. Immediately after the application has cleared SI, the TWI
will initiate transmission of the data packet.
updated with a status code indicating that the data packet has successfully been sent.
The status code will also reflect whether a slave acknowledged the packet or not.
data packet was successfully transmitted, and that the value of the ACK bit was as
expected. If SSCS indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to SSCON, instructing the TWI hardware to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the SI bit is cleared in the value written. The TWI will not start any opera-
tion as long as the SI bit in SSCON is set. Immediately after the application has cleared
SI, the TWI will initiate transmission of the STOP condition. Note that SI is NOT set
after a STOP condition has been sent.
3722A–MICRO–10/11