AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 198

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 24-10. FCON – Flash Control Register
Table 24-11.
198
FCON Address = 0D1H
Not Bit Addressable
Symbol
FPL
FPS
FMOD
FBUSY
Symbol
FOUT
AERS
LDPG
FLGE
INHIBIT
ERR
Bit
3-0
EECON = D2H
Not Bit Addressable
Bit
1-0
AT89LP51RB2/RC2/IC2 Preliminary
FPL3
Function
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD
Flash Map Program Space
Set this bit to direct the MOVX @DPTR, A and MOVX @/DPTR, A instructions to the Flash memory temporary page
buffer. Clear to allow MOVX to write regular data memory.
Flash Mode
Mode
Flash Busy
Set by hardware when programming is in progress. Cleared by hardware when programming is done. Cannot be
changed by software.
Function
When FLGE = 1, FOUT is set/cleared by hardware during reads from EDATA in the range of 0780H–07FFH to show the
byte flag status of the last location accessed. FOUT = 1 when FLGE = 0.
Auto-Erase Enable. Set to perform an auto-erase of a Flash memory page during the next write sequence. Clear to
perform write without erase. This bit is reserved for the Flash API.
Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded
more than once before a write. LDPG must be cleared before writing.
Byte Flag Enable. When FLGE = 1, writes to EDATA in the range of 0780H–07FFH will set the byte flag of the location
accessed. Reads in the range of 0780H–07FFH will return the byte flag status in FOUT. When FLGE = 0 all byte flags
are reset to zero.
Write Inhibit Flag. Cleared by hardware when the voltage on VDD has fallen below the minimum programming voltage.
Set by hardware when the voltage on VDD is above the minimum programming voltage (after 2 ms delay).
Error Flag. Set by hardware if an error occurred during the last programming sequence (Flash or EEPROM) due to a
brownout condition (low voltage on VDD). Must be cleared by software.
7
EECON
FOUT
0
1
2
3
7
– EEPROM Control Register
FMOD1
FPL2
0
0
1
1
6
AERS
6
FMOD0
0
1
0
1
FPL1
5
LDPG
Memory Operation Target
CODE space (0000–FFFFH)
User Signature space (0000–01FFH)
Atmel Signature space (0200–027FH read-only)
User Fuse space (0000–007FH)
Hardware Security space (0080–00FFH read-only)
Reserved
5
FPL0
4
FLGE
4
FPS
3
INHIBIT
3
FMOD1
1-0
2
ERR
.
2
Reset Value = xxxx 000xB
FMOD0
Reset Value = 1000 XXXB
1
–
1
FBUSY
3722A–MICRO–10/11
0
–
0