AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 84

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

13.6.1
13.6.2
84
AT89LP51RB2/RC2/IC2 Preliminary
Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler
Mode 1 – 8-bit PWM with 8-bit Linear Prescaler
In Mode 0, TLn acts as a logarithmic prescaler driving 8-bit counter THn (see
PSCn bits in TCONB control the prescaler value. On THn overflow, the duty cycle value in RHn
is transferred to OCRn and the output pin is set high. When the count in THn matches OCRn,
the output pin is cleared low. The following formulas give the output frequency and duty cycle for
Timer n in PWM Mode 0. Timer 1 in PWM Mode 0 is identical to Timer 0.
Note:
Figure 13-6. Timer/Counter 1 PWM Mode 0
In Mode 1, TLn provides linear prescaling with an 8-bit auto-reload from RLn (see
page
On THn overflow, the duty cycle value in RHn is transferred to OCRn and the output pin is set
high. When the count in THn matches OCRn, the output pin is cleared low. The following formu-
las give the output frequency and duty cycle for Timer n in PWM Mode 1. Timer 1 in PWM Mode
1 is identical to Timer 0.
Note:
85). On TLn overflow, TLn is loaded with the value of RLn. THn acts as an 8-bit counter.
INT1 Pin
In Fast Mode, TPS applies only when the TnX2 bits in CKCON0 are set. TPS always
applies in Compatibility Mode, therefore setting TnX2 in Compatibility Mode will halve
the output frequency.
In Fast Mode, TPS applies only when the TnX2 bits in CKCON0 are set. TPS always
applies in Compatibility Mode, therefore setting TnX2 in Compatibility Mode will halve
the output frequency.
GATE1
CLK
SYS
TR1
Mode 1:
Mode 0:
÷TPS
Control
f
out
f
out
Duty Cycle %
Duty Cycle %
=
=
------------------------------------------------ -
256
PSC1
---------------------------------------- -
256
×
×
(8 Bits)
(
f
f
TL1
256 RLn
SYS
SYS
2
PSCn
=
–
=
100
100
+
1
(8 Bits)
(8 Bits)
OCR1
×
RH1
)
TH1
×
×
×
-------------------- -
TPS
RHn
----------- -
RHn
----------- -
256
256
-------------------- -
TPS
1
=
1
+
+
1
1
Figure
3722A–MICRO–10/11
Figure 13-7 on
13-6). The
T1