AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 46

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

6.6.4
Table 6-4.
Table 6-5.
6.7
46
CKS
SCLKT0
OscBEn
OscAEn
Symbol
Symbol
CKSEL = 85H (AT89LP51IC2 Only)
Not Bit Addressable
Bit
OSCCON = 86H (AT89LP51IC2 Only)
Not Bit Addressable
Bit
X1/X2 Feature
AT89LP51RB2/RC2/IC2 Preliminary
Registers
Function
Clock Select. Clear CKS to connect the system clock (CPU and peripherals) to the OSCB source. Set CKS to connect
the system clock to the OSCA source. The default state is set by the Oscillator Select user fuse. See
page
Function
Sub Clock Timer 0. Clear to connect the Timer 0 counter input to T0 (P3.4). Set to connect the Timer 0 counter input to
OSCB output divided by 128. OSCB must be sourced from crystal oscillator B to use this feature.
OSCB Enable. Clear to power down the OSCB source. Set to enable the OSCB source. The default state is set by the
Oscillator Select user fuse. See
will free the XTAL1B and XTAL2B pins for use as P1.0 and P4.2.
OSCA Enable. Clear to power down the OSCA source. Set to enable the OSCA source. The default state is set by the
Oscillator Select user fuse. See
CKSEL
OSCCON
–
7
–
7
188.
– Clock Selection Register
– Oscillator Control Register
The AT89LP51RB2/RC2/IC2 includes the X1/X2 feature for compatibility with the existing
AT89C51RB2/RC2/IC2. This feature allows a divider-by-2 to be switched in/out between the
oscillator source and the main system clock. This feature is controlled by the X2 bit in CKCON0
(See
source, ensuring a 50% duty cycle regardless of the cyclic ratio at the oscillator output. When
X2 = 1 the oscillator output is passed through with no division. In this case the duty cycle at the
oscillator must be between 40% and 60%. Note that the naming convention can be confusing
since X1 means divide-by-2 and X2 means divide-by-1 as shown in
of the X2 bit is set by the X2 User fuse (See
changed by software. This fuse is also shadowed in the X2 bit of the bootloader Hardware Secu-
rity Byte (HSB). Note that the fuse/HSB bit is inverted from the control bit in the CKCON0 SFR.
Table 6-6.
Mode
X1
X2
–
6
–
6
Table 6-9 on page
X1/X2 Modes
Section 24.2 on page
Section 24.2 on page
(CKCON0.0)
–
5
–
5
X2
0
1
48). When X2 = 0 the system clock is divided by two from the oscillator
–
4
–
4
f
f
CPU Clock
CPU
CPU
188. OscBEn cannot be disabled when CKS = 0. Disabling OSCB
188. OscAEn cannot be disabled when CKS = 1.
= f
= f
SYS
SYS
/2
/1
–
3
–
3
Section 24.2 on page
Duty Cycle
No limits
40–60%
XTAL1
SCLKT0
–
2
2
Reset Value = XXXX XXX?B
Reset Value = XXXX X0??B
(HSB.X2)
X2 Fuse
FFH (1)
00H (0)
OscBEn
Table
–
1
1
188) but can always be
6-7. The default state
Section 24.2 on
OscAEn
3722A–MICRO–10/11
CKS
0
0