AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 57

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

8.2.2
8.3
3722A–MICRO–10/11
Reducing Power Consumption
Reset Recovery from Power-down
Figure 8-2.
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought low.
Figure 8-3.
Several possibilities need consideration when trying to reduce the power consumption in an
8051-based system.
• Idle or Power-down mode should be used as often as possible with interrupts waking up the
• All un-needed peripheral functions should be disabled
• The System Clock Prescaler can scale down the operating frequency during periods of low
• The ALE output can be disabled by setting AO in AUXR, thereby also reducing EMI
• For AT89LP51IC2, switch the system clock from a high power oscillator like XTALA to a lower
system to handle specific tasks
demand (See
power oscillator like the internal 8 MHz oscillator during periods when frequency accuracy is
not as important.
Internal
Internal
Internal
XTAL1
XTAL1
Reset
Clock
Clock
PWD
PWD
INT1
RST
Interrupt Recovery from Power-down (PWDEX = 0)
Reset Recovery from Power-down (POL = 1)
“System Clock Prescaler” on page
Table 7-1 on page
AT89LP51RB2/RC2/IC2 Preliminary
Figure
52). If RST returns low before the time-out, a two
t SUT
47.)
8-3. The internal clock will not be allowed to
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