AT89LP51RB2 Atmel Corporation, AT89LP51RB2 Datasheet - Page 31

• Manufacturer Part Number: AT89LP51RB2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RB2

• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

5. Enhanced CPU
5.1
3722A–MICRO–10/11
Fast Mode
The AT89LP51RB2/RC2/IC2 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed
of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in perfor-
mance is due to two factors. First, the CPU fetches one instruction byte from the code memory
every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute
instructions in parallel. This basic pipelining concept allows the CPU to obtain up to
1 MIPS per MHz. The AT89LP51RB2/RC2/IC2 also has a Compatibility mode that preserves the
12-clock machine cycle of standard 8051s like the AT89C51RB2/RC2/IC2.
Fast (Single-Cycle) mode must be enabled by clearing the Compatibility User Fuse. (See
Configuration Fuses” on page
clock cycle. The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes.
In a single-clock-per-byte-fetch system this means each instruction takes at least as many
clocks as it has bytes to execute. The majority of instructions in the AT89LP51RB2/RC2/IC2 fol-
low this rule: the instruction execution time in system clock cycles equals the number of bytes
per instruction, with a few exceptions. Branches and Calls require an additional cycle to com-
pute the target address and some other complex instructions require multiple cycles.
“Instruction Set Summary” on page 173.
Example of Fast mode instructions are shown in
take three times as long to execute if they are fetched from external program memory.
Figure 5-1.
Instruction Execution Sequences in Fast Mode
(A) 1-byte, 1-cycle instruction, e.g. INC A
(B) 2-byte, 2-cycle instruction, e.g. ADD A, #data
(C) 1-byte, 2-cycle instruction, e.g. INC DPTR
(D) MOVX (1-byte, 4-cycle)
CLK
AT89LP51RB2/RC2/IC2 Preliminary
188.) In this mode one instruction byte is fetched every system
S1
S1
S1
S1
for more detailed information on individual instructions.
ACCESS EXTERNAL
ADDR
READ NEXT
OPCODE
READ OPERAND
S2
S2
S2
MEMORY
READ NEXT OPCODE
READ NEXT OPCODE
S3
Figure
DATA
S4
5-1. Note that Fast mode instructions
READ NEXT
OPCODE
“User
See
31