AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 136

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.25.7
Table 12-14.
136
PASDLKn2
0
0
0
0
AT90PWM81
PSC 2 Extended Configuration Register – PCNFE2
Analog signal synchronization or Input Blanking Mode Selection
PASDLKn1
0
0
1
1
• Bit 4:3 – PMODEn1: 0: PSC n Mode
Select the mode of PSC.
Table 12-13.
• Bit 2 – POPn: PSC n Output Polarity
If this bit is cleared, the PSC outputs are active Low.
If this bit is set, the PSC outputs are active High.
• Bit 1 – PCLKSELn: PSC n Input Clock Select
This bit is used to select between CLKPF or CLKPS clocks.
Set this bit to select the fast clock input (CLKPF).
Clear this bit to select the slow clock input (CLKPS).
• Bit 0 – POME2: PSC 2 Output Matrix Enable (PSC2 only)
Set this bit to enable the Output Matrix feature on PSC2 outputs. See
When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.
The PSC n Extended Configuration Register is used to configure the running mode of the PSC
• Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking select
Defines the modes for Analog signal synchronization delay or Input Blanking.
Bit
Read/Write
Initial Value
PMODEn1
0
0
1
1
PASDLKn0
0
1
0
1
7
PASDLKn2 PASDLKn1 PASDLKn0 PBFMn1
R/W
0
PSC n Mode Selection
PMODEn0
0
1
0
1
6
R/W
0
Description
No Analog signal synchronization delay, no Input Blanking
No Analog signal synchronization delay , Input Blanking using PSC clock, started
on PSC end of cycle
No Analog signal synchronization delay , Input Blanking using PSC clock, started
on OCR SA event
No Analog signal synchronization delay , Input Blanking using PSC clock, started
on OCR SB event
5
R/W
0
One Ramp Mode
Two Ramp Mode
Four Ramp Mode
Center Aligned Mode
Description
4
R/W
0
3
PELEVnA1 PELEVnB1 PISELnA1 PISELnB1 PCNFE2
0
R/W
2
R/W
0
“PSC2 Outputs” on page
1
R/W
0
0
R/W
0
7734P–AVR–08/10
129.