AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 188

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.5.2
14.5.3
188
AT90PWM81
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set
and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this
will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt han-
dling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set,
then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit
(and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing
the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Mas-
ter mode (see
When the SPI is configured as Slave, the SPI is only guaranteed to work at f
The SPI interface on the AT90PWM81 is also used for program memory and EEPROM downloading or
uploading. See
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI
Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift
Register Receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Table
7
SPD7
R/W
X
7
SPIF
R
0
Serial Programming Algorithm261
14-5). This means that the minimum SCK period will be two CPU clock periods.
6
SPD6
R/W
X
6
WCOL
R
0
5
SPD5
R/W
X
5
–
R
0
4
SPD4
R/W
X
4
–
R
0
for serial programming and verification.
3
SPD3
R/W
X
3
–
R
0
2
SPD2
R/W
X
2
–
R
0
1
SPD1
R/W
X
1
–
R
0
clkio
/4 or lower.
0
SPD0
R/W
X
0
SPI2X
R/W
0
7734P–AVR–08/10
SPDR
Undefined
SPSR