AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 238

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

20.5.1
238
AT90PWM81
Store Program Memory Control and Status Register – SPMCSR
The Store Program Memory Control and Status Register contains the control bits needed to control the
Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready inter-
rupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR
Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the
RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be
accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming
operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load opera-
tion is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles
will read a byte from the signature row into the destination register. see
Software243“ for details.
An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This opera-
tion is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for
reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must
wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written
to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the
RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a
Page Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load
operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in
the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit
set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will
read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register.
See
• Bit 2 – PGWRT: Page Write
Bit
Read/Write
Initial Value
“Reading the Fuse and Lock Bits from Software” on page 242
7
SPMIE
R/W
0
6
RWWSB
R
0
5
SIGRD
R/W
0
4
RWWSRE
R/W
0
3
BLBSET
R/W
0
2
PGWRT
R/W
0
for details.
Reading the Signature Row from
1
PGERS
R/W
0
0
SPMEN
R/W
0
7734P–AVR–08/10
SPMCSR