ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 176
ATmega64M1
Manufacturer Part Number
ATmega64M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega64M1
Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega64M1-15MD
Manufacturer:
ATMEL
Quantity:
700
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19.7
19.7.1
19.7.2
19.7.3
19.7.4
176
CAN Timer
ATmega16M1/32M1/64M1
Prescaler
16-bit Timer
Time Triggering
Stamping Message
The data index (INDX) is the address pointer to the required data byte. The data byte can be
read or write. The data index is automatically incremented after every access if the AINC* bit is
reset. A roll-over is implemented, after data index=7 it is data index=0.
The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1,
...
A programmable 16-bit timer is used for message stamping and time trigger communication
(TTC).
Figure 19-11. CAN Timer Block Diagram
An 8-bit prescaler is initialized by CANTCON register. It receives the clk
8. It provides clk
T
This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When
the timer rolls over from 0xFFFF to 0x0000, an interrupt is generated (OVRTIM).
Two synchronization modes are implemented for TTC (TTC bit):
In TTC mode, a frame is sent once, even if an error occurs.
The capture of the timer value is done in the MOb which receives or sends the frame. All man-
aged MOb are stamped, the stamping of a received (sent) frame occurs on RxOk (TXOK).
RXOK[i]
clk
TXOK[i]
clk
CANTIM
– synchronization on Start of Frame (SYNCTTC=0)
– synchronization on End of Frame (SYNCTTC=1)
IO
OVRTIM
=
T
clk
CANTIM
8
IO
CANSTM[i]
x 8 x (CANTCON [7:0] + 1)
overrun
frequency to the CAN Timer if the CAN controller is enabled.
CANTCON
CANTIM
clk
CANTIM
ENFG
CANTTC
IO
TTC
frequency divided by
SYNCTTC
8209D–AVR–11/10
"EOF "
"SOF "
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