ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 186

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ATmega64M1

Manufacturer Part Number
ATmega64M1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64M1

Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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19.10.6
19.10.7
19.10.8
186
ATmega16M1/32M1/64M1
CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers
CANSIT2 and CANSIT1 – CAN Status Interrupt MOb Registers
CANBT1 – CAN Bit Timing Register 1
• Bits 5:0 - IEMOB[5:0]: Interrupt Enable by MOb
Note:
• Bit 15:6 –Res: Reserved
These bits are reserved for future use. For compatibility with future devices, it must be written to
zero when CANIE1 & CANIE2 are written.
• Bits 5:0 - SIT[5:0]: Status of Interrupt by MOb
Note:
• Bit 15:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
Read/Write
Initial Value
Read/Write
Initial Value
Read/Write
Initial Value
Read/Write
Initial Value
Initial Value
Read/Write
– 0 - interrupt disabled
– 1 - MOb interrupt enabled
– 0 - no interrupt
– 1- MOb interrupt
Bit
Bit
Bit
Bit
Bit
Example: CANIE2 = 0000 1100
Example: CANSIT2 = 0010 0001
R/W
15
15
R
R
R
7
0
0
7
0
0
7
-
-
-
-
-
-
-
BRP5
R/W
R/W
R/W
14
14
R
R
6
0
0
6
0
0
6
0
-
-
-
-
IEMOB5
BRP4
SIT5
R/W
R/W
R/W
13
13
R
R
5
0
0
5
0
0
5
0
-
-
b
b
: enable of interrupts on MOb 2 and 3
: MOb 0 and 5 interrupts
IEMOB4
BRP3
SIT4
R/W
R/W
R/W
12
12
R
R
4
0
0
4
0
0
-
-
4
0
IEMOB3
BRP2
SIT3
R/W
R/W
R/W
11
11
R
R
3
0
0
3
0
0
3
0
-
-
IEMOB2
BRP1
SIT2
R/W
R/W
R/W
10
10
R
R
2
0
0
2
0
0
2
0
-
-
IEMOB1
BRP0
SIT1
R/W
R/W
R/W
R
R
1
9
0
0
1
9
0
0
-
-
1
0
IEMOB0
SIT0
R/W
R/W
R
R
0
8
0
0
0
8
0
0
0
-
-
-
-
-
8209D–AVR–11/10
CANSIT2
CANSIT1
CANBT1
CANIE2
CANIE1

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