ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 181

• Manufacturer Part Number: ATmega64M1
• Manufacturer: Atmel Corporation

Specifications of ATmega64M1

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.10.1
8209D–AVR–11/10
CANGCON – CAN General Control Register
• Bit 7 – ABRQ: Abort Request
This is not an auto resettable bit.
• Bit 6 – OVRQ: Overload Frame Request
This is not an auto resettable bit.
The overload frame can be traced observing OVFG in CANGSTA register (c.f.
page
• Bit 5 – TTC: Time Trigger Communication
• Bit 4 – SYNTTC: Synchronization of TTC
This bit is only used in TTC mode.
• Bit 3 – LISTEN: Listening Mode
• Bit 2 – TEST: Test Mode
Note:
• Bit 1 – ENA/STB: Enable / Standby Mode
Because this bit is a command and is not immediately effective, the ENFG bit in CANGSTA reg-
ister gives the true state of the chosen mode.
Initial Value
Read/Write
– 0 - no request
– 1 - abort request: a reset of CANEN1 and CANEN2 registers is done. The pending
– 0 - no request
– 1 - overload frame request: send an overload frame after the next received frame
172).
– 0 - no TTC
– 1 - TTC mode
– 0 - the TTC timer is caught on SOF
– 1 - the TTC timer is caught on the last bit of the EOF
– 0 - no listening mode
– 1 - listening mode
– 0 - no test mode
– 1 - test mode: intend for factory testing and not for customer use
Bit
communications are immediately disabled and the on-going one will be normally
terminated, setting the appropriate status flags
Note that CANCDMOB register remain unchanged
CAN may malfunction if this bit is set
ABRQ
R/W
7
0
OVRQ
R/W
6
0
TTC
R/W
5
0
SYNTTC
R/W
4
0
ATmega16M1/32M1/64M1
LISTEN
R/W
3
0
TEST
R/W
2
0
ENA/STB
R/W
1
0
SWRES
R/W
0
0
Figure 19-9 on
CANGCON
181