ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 28

• Manufacturer Part Number: ATmega64M1
• Manufacturer: Atmel Corporation

Specifications of ATmega64M1

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.1.4
8.1.5
8.2
28
Clock Sources
ATmega16M1/32M1/64M1
PLL Clock – clk
ADC Clock – clk
The PLL clock allows the fast peripherals to be clocked directly from a 64/32MHz clock. A
16MHz clock is also derived for the CPU.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as illustrated
Table 8-1. The clock from the selected source is input to the AVR clock generator, and routed to
the appropriate modules.
Table 8-1.
Note:
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before starting
normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up
time. The number of WDT Oscillator cycles used for each time-out is shown in
29. The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.
PLL
ADC
Device Clocking Option
External Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
Reserved
Reserved
PLL output divided by 4 : 16 MHz
Calibrated Internal RC Oscillator
PLL output divided by 4 : 16 MHz / PLL driven by External
clock
External Clock
1. For all fuses “1” means unprogrammed while “0” means programmed
2. Ext Osc: External Osc
3. RC Osc: Internal RC Oscillator
4. Ext Clk: External Clock Input
Device Clocking Options Select
(1)
System
Clock
Ext Osc
Ext Osc
PLL/4
N/A
N/A
PLL/4
RC Osc
PLL/4
Ext Clk
PLL Input
RC Osc
Ext Osc
Ext Osc
N/A
N/A
RC Osc
RC Osc
Ext Clk
RC Osc
Table 8-2 on page
8209D–AVR–11/10
1111 - 1000
CKSEL3..0
0100
0101
0110
0111
0011
0010
0001
0000