ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 249

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.10 INTCTRLB – Interrupt Control Register B
20.13.11 INTFLAGSACLR/ INTFLAGSASET – Clear/ Set Interrupt Flag Register A
8331A–AVR–07/11
• Bit 5 – BUSERRIE: Bus Error Interrupt Enable
Setting this bit will enable the interrupt for the following three different bus error events:
The INTLVL bits must be non-zero for the interrupts to be generated.
• Bit 4 – STALLIE: STALL Interrupt Enable
Setting this bit enables the STALL interrupt for the conditions that sets the Stall Interrupt Flag
(STALLIF) in the INTFLAGSACLR/SET register. The INTLVL bits must be non-zero for the inter-
rupts to be generated.
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enables the USB interrupts and select the interrupt level as described in
and Programmable Multilevel Interrupt Controller” on page
source must be separately enabled.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – TRNIE: Transaction Complete Interrupt Enable
Setting this bit enables the Transaction Complete Interrupt for IN and OUT transactions. The
INTLVL bits must be non-zero for interrupts to be generated.
• Bit 0 – SETUPIE: SETUP Transaction Complete Interrupt Enable
Setting this bit enables the SETUP Transaction Complete Interrupt for SETUP transactions. The
INTLVL bits must be non-zero for the interrupts to be generated.
This register is mapped into two I/O memory locations, one for clearing (INTFLAGSACLR) and
one for setting the flags (INTFLAGSASET). The individual flags can be set by writing a one to its
bit location in INFLAGSASET, and cleared by writing a one to its bit location in INTFLAGSACLR.
Bit
+0x07
Read/Write
Initial Value
1. Isochronous CRC Error: An interrupt will be generated for the conditions that set CRC
2. Underflow: An interrupt will be generated for the conditions that set the Undeflow Inter-
3. Overflow: An interrupt will be generated for the conditions that set the Overflow Inter-
Interrupt Flag (CRCIF) in the INTFLAGSACLR/SET register during isochronous
transfers.
rupt Flag (UNFIF) in the INTFLAGSACLR/SET register.
rupt Flag (OVFIF) in the INTFLAGSACLR/SET register.
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
Atmel AVR XMEGA AU
132. In addition each USB interrupt
R
2
–
0
TRNIE
R/W
1
0
SETUPIE
R/W
0
0
”Interrupts
INTCTRLB
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