ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 266

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.5
8331A–AVR–07/11
TWI Master Operation
Figure 21-11. Bus state, state diagram.
After a system reset and/or TWI master enable, the bus state is unknown. The bus state
machine can be forced to enter idle by writing to the bus state bits accordingly. If no state is set
by application software, the bus state will become idle when the first STOP condition is detected.
If the master inactive bus timeout is enabled, the bus state will change to idle on the occurrence
of a timeout. After a known bus state is established, only a system reset or disabling of the TWI
master will set the state to unknown.
When the bus is idle, it is ready for a new transaction. If a START condition generated externally
is detected, the bus becomes busy until a STOP condition is detected. The STOP condition will
change the bus state to idle. If the master inactive bus timeout is enabled, the bus state will
change from busy to idle on the occurrence of a timeout.
If a START condition is generated internally while in idle state, the owner state is entered. If the
complete transaction was performed without interference, i.e., no collisions are detected, the
master will issue a STOP condition and the bus state will change back to idle. If a collision is
detected, the arbitration is assumed lost and the bus state becomes busy until a STOP condition
is detected. A repeated START condition will only change the bus state if arbitration is lost dur-
ing the issuing of the repeated START. Arbitration during repeated START can be lost only if the
arbitration has been ongoing since the first START condition. This happens if two masters send
the exact same ADDRESS+DATA before one of the masters issues a repeated START (Sr).
The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate
interrupts for master write and master read. Interrupt flags can also be used for polled operation.
There are dedicated status flags for indicating ACK/NACK received, bus error, arbitration lost,
clock hold, and bus state.
(0b01)
RESET
IDLE
P + Timeout
Write ADDRESS
UNKNOWN
(S)
(0b00)
Command P
P + Timeout
OWNER
(0b10)
S
ADDRESS(Sr)
Atmel AVR XMEGA AU
Write
Arbitration
Lost
BUSY
(0b11)
Sr
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