ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 32

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8331A–AVR–07/11
• Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done
pulling th pin low will not cause an external reset. A reset is required before this bit will be read
correctly after it is changed.
• Bit 3:2 – STARTUPTIME[1:0]: Start-up time
These fuse bits can be used to set at a programmable timeout period from all reset sources are
released until the internal reset is released from the delay counter. A reset is required before
these bits will be read correctly after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to
page 112
Table 4-4.
• Bit 1 – WDLOCK: Watchdog Timer Lock
The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this
fuse is programmed the watchdog timer configuration cannot be changed, and the ENABLE bit
in the watchdog CTRL register is automatically set at reset and cannot be cleared from the appli-
cation software. The WEN bit in the watchdog WINCTRL register is not set automatically and
needs to be set from software. A reset is required before this bit will be read correctly after it is
changed.
Table 4-5.
• Bit 0 – JTAGEN: JTAG Enabled
This fuse controls whether or not the JTAG interface is enabled.
When the JTAG interface is disabled all access through JTAG is prohibited, and the device can
be accessed using the program and debug interface (PDI). The JTAGEN fuse is available on
devices with JTAG interface. A reset is required before this bit will be read correctly after it is
changed.
Table 4-6.
STARTUPTIME[1:0]
WDLOCK
JTAGEN
00
01
10
11
for details.
0
1
0
1
Start-up time.
Watchdog timer lock.
JTAG Enable
Description
Watchdog timer locked for modifications
Watchdog timer not locked
Description
JTAG enabled
JTAG disabled
1kHz ULP Oscillator Cycles
Atmel AVR XMEGA AU
Reserved
64
4
0
”Reset Sequence” on
32