ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 335

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.5.5
27.5.6
27.6
27.6.1
27.6.2
8331A–AVR–07/11
SRAM LPC Configuration
Address Latch Requirements
Timing
Multiplexing Data with Address Byte 0
Multiplexing Data with Address Byte 0 and 1
The Address Latch timing and parameter requirements are described in EBI Timing. See the
device datasheet characteristics for details.
SRAM or external memory devices may have different timing requirements. To meet these vary-
ing requirements, each Chip Select can be configured with different wait-states. Timing details is
described the device datasheet.
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing
modes where the data and address lines are multiplexed. Compared to SRAM configuration,
this can further reduce the number of pins required for the EBI. The available configurations is
shown in
Address Byte 0 and 1” on page
Timing and Address Latch requirements is as for SRAM configuration.
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same
port, and the ALE1 signal from the device controls the address latch.
Figure 27-7. Multiplexed SRAM LPC connection using ALE1
When the data byte and address byte 0 (AD[7:0]), and address byte 1 (A[15:8]) are multiplexed,
they are output from the same port, and the ALE1 and ALE2 signal from the device control the
external address latches.
”Multiplexing Data with Address Byte 0” on page 335
EBI
A[19:16]
AD[7:0]
A[15:8]
ALE1
335.
D
G
Atmel AVR XMEGA AU
Q
D[7:0]
A[7:0]
A[15:8]
A[19:16]
through
SRAM
”Multiplexing Data with
335