ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 288

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.7.2
22.7.3
8331A–AVR–07/11
INTCTRL – Interrupt Control Register
STATUS – Status Register
Table 22-3.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable the SPI interrupt and select the interrupt level, as described in
Programmable Multilevel Interrupt Controller” on page
gered when IF in the STATUS register is set.
• Bit 7 – IF: Interrupt Flag
This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the
DATA register. If SS is configured as input and is driven low when the SPI is in master mode,
this will also set this flag. IF is cleared by hardware when executing the corresponding interrupt
vector. Alternatively, the IF flag can be cleared by first reading the STATUS register when IF is
set, and then accessing the DATA register.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
CLK2X
0
0
0
0
1
1
1
1
IF
7
–
R
0
R
7
0
Relationship between SCK and the peripheral clock (Clk
WRCOL
6
–
R
0
R
6
0
PRESCALER[1:0]
R
R
5
–
0
5
–
0
00
01
10
11
00
01
10
11
R
R
4
–
0
4
–
0
Atmel AVR XMEGA AU
R
R
3
–
0
3
–
0
SCK Frequency
Clk
Clk
Clk
Clk
Clk
Clk
Clk
Clk
PER
PER
PER
PER
PER
PER
PER
PER
132. The enabled interrupt will be trig-
/4
/16
/64
/128
/2
/8
/32
/64
R
R
2
–
0
2
–
0
R/W
PER
R
1
0
1
–
0
INTLVL[1:0]
) frequency.
R/W
R
0
0
”Interrupts and
0
–
0
INTCTRL
STATUS
288