ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 48

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.20.8
4.20.9
8331A–AVR–07/11
EVSYSLOCK – Event System Lock Register
AWEXLOCK – Advanced Waveform Extension Lock Register
ule is enabled. This reduces the peak current consumption during startup of the module. For
maximum effect the start-up delay should be set so that it is larger than 0.5µs.
Table 4-13.
• Bit 7:5 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 4 – EVSYS1LOCK:
Setting this bit will lock all registers in the event system related to event channels 4 to 7 further
modification. The following registers in the event system are locked: CH4MUX, CH4CTRL,
CH5MUX, CH5CTRL, CH6MUX, CH6CTRL, CH7MUX, CH7CTRL. This bit is protected by the
configuration change protection mechanism or details refer to
on page
• Bit 3:1 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 – EVSYS0LOCK:
Setting this bit will lock all registers in the event system related to event channels 0 to 3 further
modification. The following registers in the event system are locked: CH0MUX, CH0CTRL,
CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, CH3CTRL. This bit is protected by the
configuration change protection mechanism or details refer to
on page
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
STARTUPDLYx
00
11
10
11
12.
12.
Analog startup delay.
R
7
–
0
7
–
R
0
Group Configuration
R
6
–
0
R
6
–
0
32CLK
NONE
2CLK
8CLK
R
5
–
0
R
5
–
0
EVSYS1LOCK
R
4
–
0
R/W
4
0
Description
Direct startup
2 * CLK
8 * CLK
32 * CLK
R
3
–
0
PER
PER
Atmel AVR XMEGA AU
R
3
–
0
PER
AWEXELOCK
R/W
2
0
R
2
–
0
”Configuration Change Protection”
”Configuration Change Protection”
1
–
R
0
R
1
–
0
AWEXCLOCK
EVSYS0LOCK
R/W
R/W
0
0
0
0
AWEX_LOCK
EVSYSLOCK
48