ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 18

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
Table 2. Hardware Register Map
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1
Address
000Ch
000Dh
001Ch
001Dh
000Ah
000Bh
000Eh
000Fh
001Ah
001Bh
001Eh
001Fh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
0020h
0021h
0022h
0023h
LINSCI™
Port G
Block
Port A
Port B
Port C
Port D
Port E
Port H
Port F
SPI
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
PGDDR
PGOR
PHDR
PHDDR
PHOR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
SPIDR
SPICR
SPICSR
Register
Label
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
Port G Data Register
Port G Data Direction Register
Port G Option Register
Port H Data Register
Port H Data Direction Register
Port H Option Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Reserved Area (1 Byte)
Register Name
Status
Reset
00h
00h
00h
00h
00h
00h
00h
00h
C0h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0xh
00h
xxh
xxh
xxh
1)
1)
1)
1)
1)
1)
1)
1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
2)
2)
2)