ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 147

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
15.7
15.7.1
Table 72.
SCI registers
Status register (SCISR)
Table 73.
Idle Line Detected
Parity Error
SCISR
Bit
7
6
5
TDRE
RO
7
RDRF
Name
TDRE
TC
Interrupt event
SCI interrupt control/wake-up capability
SCISR register description
Transmit data register empty
Transmission complete
Received data ready flag
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR
register followed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register unless the TDRE bit is cleared.
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared
by a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
RO
TC
6
RDRF
RO
5
Doc ID 13829 Rev 1
Event flag
IDLE
PE
IDLE
RO
4
Enable control
Function
OR
RO
Serial communications interface (SCI)
3
ILIE
PIE
bit
RO
NF
2
Reset value: 1100 0000 (C0h)
Exit from
Wait
Yes
Yes
RO
FE
1
Exit from
Halt
No
No
147/243
RO
PE
0