ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 84

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Main clock controller with real-time clock and beeper (MCC/RTC)
11.8
11.8.1
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Main clock controller registers
MCC control/status register (MCCSR)
Table 40.
MCCSR
Bit
6:5 CP[1:0]
3:2
7
4
1
MCO
RW
7
TB[1:0]
Name
MCO
SMS
OIE
MCCSR register description
Main clock out selection
CPU clock prescaler
Slow mode select
Time base control
Oscillator interrupt enable
This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f
Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.
These bits select the CPU clock prescaler which is applied in the different slow
modes. Their action is conditioned by the setting of the SMS bit. These two bits are
set and cleared by software.
00: f
01: f
10: f
11: f
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
real-time clock and beeper (MCC/RTC)
These bits select the programmable divider time base. They are set and cleared by
software (see
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base
as a real-time clock.
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active Halt
power saving mode .
6
CP[1:0]
Section 8.2: Slow mode on page 62
CPU
CPU
CPU
CPU
RW
in Slow mode = f
in Slow mode = f
in Slow mode = f
in Slow mode = f
5
Table
Doc ID 13829 Rev 1
CPU
CPU
is given by CP1, CP0
41) .
= f
SMS
RW
OSC2
4
OSC2
OSC2
OSC2
OSC2
/2
/4
/8
/16
Function
CPU
3
for more details.
and
on I/O port)
TB[1:0]
RW
Chapter 11: Main clock controller with
2
Reset value: 0000 0000 (00h)
OIE
RW
1
ST72321xx-Auto
OIF
RW
0