ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 65

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
8.4
8.4.1
Note:
Caution:
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register) as shown in
Table 27.
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see
more details on the MCCSR register).
The MCU can exit Active Halt mode on reception of an MCC/RTC interrupt or a RESET.
When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay
occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector
which woke it up (see
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register
must not be cleared before t
delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining
t
DELAY
MCCSR OIE bit
period.
0
1
MCC/RTC low power mode selection
Table
Figure
Power saving mode entered when HALT instruction is executed
27.
DELAY
26).
Doc ID 13829 Rev 1
after the interrupt occurs (t
Section 12.3: ART registers on page 93
Active Halt
Halt
DELAY
= 256 or 4096 t
Power saving modes
CPU
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