ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 240

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Known limitations
22.1.9
22.1.10
22.1.11
22.2
22.2.1
22.3
22.3.1
240/243
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs, the output
compare flag then gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If the output compare interrupt is enabled, then the output compare flag cannot be cleared in
the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer, then the timer interrupts.
●
●
I
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a restart and Slave address to re-initiate communication.
Readout protection with LVD
The LVD is not supported if readout protection is enabled
All Flash devices
Internal RC oscillator with LVD
The internal RC can only be used if LVD is enabled.
Limitations specific to ROM devices
LVD operation
Depending on the operating conditions, especially the V
temperature, in some cases the LVD may not start. When this occurs, the MCU may operate
outside the guaranteed functional area (see
In this case, proper use of the watchdog may make it possible to recover through a
watchdog reset and allow normal operations to resume.
2
C multimaster
Perform the following to disable the timer:
–
–
Perform the following to enable the timer again:
–
–
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
TACSR & or TBCSR & = ~0x40; // Enable the timer
TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
Doc ID 13829 Rev 1
Figure
73) without being forced into reset state.
DD
ramp up speed and ambient
ST72321xx-Auto