ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 166

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

I2C bus interface (I2C)
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Table 84.
Bit
6
5
4
3
2
ADD10
Name
BUSY
ADSL
TRA
BTF
SR1 register description (continued)
10-bit addressing in Master mode
Transmitter/Receiver
Bus busy
Byte transfer finished
Address matched (Slave mode)
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the
peripheral is disabled (PE = 0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the
interface is disabled (PE = 0).
0: Data byte received (if BTF = 1)
1: Data byte transmitted
This bit is set by hardware on detection of a Start condition and cleared by hardware
on detection of a Stop condition. It indicates a communication in progress on the
bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This
can have consequences when operating in Multimaster mode; that is, a second
active I
conflict resulting in lost data. A software workaround consists of checking that the
I
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE = 1. It is cleared by software reading SR1 register
followed by a read or write of DR register. It is also cleared by hardware when the
interface is disabled (PE = 0).
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event (see
Figure
in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the
byte from DR register.
The SCL line is held low while BTF = 1.
0: Byte transfer not done
1: Byte transfer succeeded
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if
ITE = 1. It is cleared by software reading SR1 register or by hardware when the
interface is disabled (PE = 0).
The SCL line is held low while ADSL = 1.
0: Address mismatched or not received
1: Received address matched
2
C is not busy before enabling the I
68). BTF is cleared by reading SR1 register followed by writing the next byte
2
C master commencing a transfer with an unset BUSY bit can cause a
Doc ID 13829 Rev 1
2
Function
C Multimaster cell.
ST72321xx-Auto