TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 444

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.16
Operation in Each Mode
12.16.1.3
(1)
Transmit and Receive (Full duplex)
SCLK Output Mode
・ If SCxMOD2<WBUF> is set to "0" and the double buffers are disabled
・ If SCxMOD2<WBUF> is set to "1" and the double buffers are enabled
rupt is generated. Concurrently, 8 bits of data written to the transmit buffer are outputted
from the TXD pin, the INTTXx transmit interrupt is generated when transmission of all da-
ta bits has been completed. Then, the SCLK output stops.
ceive buffer and the next transmit data is written to the transmit buffer by the CPU. The or-
der of reading the receive buffer and writing to the transmit buffer can be freely deter-
mined. Data transmission is resumed only when both conditions are satisfied.
the INTRXx interrupt is generated. While 8 bits of data is received, 8 bits of transmit data
is outputted from the TXD pin. When all data bits are sent out, the INTTXx interrupt is gen-
erated and the next data is moved from the transmit buffer to the transmit shift register.
(SCxMOD2<TBEMP> = 1) or when the receive buffer is full (SCxMOD2<RBFULL> =
1), the SCLK output is stopped. When both conditions, receive data is read and transmit da-
ta is written, are satisfied, the SCLK output is resumed and the next round of data transmis-
sion and reception is started.
SCLK is outputted when the CPU writes data to the transmit buffer.
Subsequently, 8 bits of data are shifted into receive buffer and the INTRXx receive inter-
The next round of data transmission and reception starts when the data is read from the re-
SCLK is outputted when the CPU writes data to the transmit buffer.
8 bits of data are shifted into the receive shift register, moved to the receive buffer, and
If the transmit buffer has no data to be moved to the transmit buffer
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TMPM364F10FG