TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 561

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.4.7
31
30-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
CANTRS<TRSx> bits of the mailboxes configured for transmission. The CANTRS<TRSx> bits of the mailbox-
es configured for reception cannot be set.
mit request is reset by setting the CANTRR<TRRx> bit to "1."
set by setting the CANTRR<TRRx> bit to "1."
−
TRS30 to TRS0
The transmission request set register can be set by a write of "1" from the CPU to only the
The CANTRS<TRSx> bit is cleared to "0" when the message has been successfully transmitted or the trans-
When transmission fails, the transmission process is repeated until it succeeds or the transmit request is re-
When the CANTRS<TRSx> bit is "1", do not write to mailbox x.
Bit Symbol
CANTRS (Transmission Request Register)
Note:Mailbox 31 is receive-only mailbox.
TRS23
TRS15
TRS7
31
23
15
0
0
0
7
0
-
R
R/W
Type
TRS30
TRS22
TRS14
TRS6
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Transmit request set (Each bit corresponds with mailboxes 30 to 0.)
Set <TRSx> requests the message transmission of corresponding mailbox x.
When transmission is requested for multiple mailboxes, the message are transmitted in accordance with
the priority corresponding to the MCR<MTOS> bit.
A write of "1" from the CPU to mailbox x configured as transmit mailbox can set the bit. A write of "0" from
the CPU is invalid.
TRS29
TRS21
TRS13
TRS5
29
21
13
0
0
0
5
0
Page 535
TRS28
TRS20
TRS12
TRS4
28
20
12
0
0
0
4
0
TRS27
TRS19
TRS11
TRS3
27
19
11
Function
0
0
0
3
0
TRS26
TRS18
TRS10
TRS2
26
18
10
0
0
0
2
0
TRS25
TRS17
TRS9
TRS1
25
17
0
0
9
0
1
0
TMPM364F10FG
TRS24
TRS16
TRS8
TRS0
24
16
0
0
8
0
0
0