TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 71

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

6.3.4
(fosc.) As a result, the input frequency to oscillator can be low, and the internal clock be made high-speed.
the CGPLLSEL<PLLSEL>. Then f
tion.
Clock Multiplication Circuit (PLL)
This circuit outputs the f
The PLL is disabled after reset. To enable the PLL, set "1" to the CGOSCCR<PLLON> bit and set "1" to
The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up func-
The following shows PLL setting sequence after reset.
The following shows the sequence of changing the PLL setting.
Note:It takes approximately 200μs for the PLL to be stabilized. A stable time for multiplier circuit is nee-
Multiplicative clock to fsys
CGOSCCR<PLLON>= “0” (PLL Stopped)
CGPLLSEL<PLLSEL>= “0” (X1 selected)
CGPLLSEL<RS,IS,C2S,ND>= “quadruple”
CGSYSCR<GEAR>= “1/1” (clock gear)
Specify the number of PLL multiplier factors
CGPLLSEL<RS,IS,C2S,ND>
CGOSCCR<PLLON>= “1” (PLL active)
CGOSCCR<PLLSEL>= “1” (PLL input)
Initial value after reset
Enable PLL operation
PLL operation selected
ded for approximately 100 μs after the number of PLL multiplier factors is changed.
Operation flow
Figure 6-2 PLL setting sequence after reset
pll
clock that is quadruple / octuple of the high-speed oscillator output clock
pll
clock output is quadruple or octuple of the high-speed oscillator (fosc).
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Need stable high-speed oscillation and
power supply voltage.
Default PLL multiplier factor is “4” .
If change the number of PLL multiplier factors,
CGOSCCR <PLLON> = “0” (PLL stop) must be
retained 100μs or more for stablization.
By setting CGOSCCR<PLLON>=” 1”→“0” (PLL stop),
multiplier factor will be initialized to “4” .
Starting PLL operation needs to approximately
200μs or more stablization time by retaining
CGOSCCR<PLLON>= “1” (PLL on).
Notes
TMPM364F10FG