TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 466

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13.4
Overview of SSP
13.4.5
DMA request is asserted.
transmit DMA request is asserted.
nals, which are asserted by the DMA controller, is provided.
clear signal is deasserted, a request signal can become active again, depending on the conditions described
above. All request signals are deasserted if the SSP is disabled or the DMA enable signal is cleared.
The DMA operation of the SSP is controlled through SSPxDMACR register.
When there are more data than the watermark level (half of the FIFO) in the receive FIFO, the receive
When the amount of data left in the transmit FIFO is less than the watermark level (half of the FIFO), the
To clear the transmit/receive DMA request, an input pin for the transmit/receive DMA request clear sig-
Set the DMA burst length to four words.
Each request signal remains asserted until the relevant DMA clear signal is asserted. After the request
The following table shows the trigger points for DMABREQ, for both the transmit and receive FIFOs.
DMA interface
Note:For the remaining three words, the SSP does not assert the burst request.
d. Overrun interrupt
interrupt is generated immediately after transfer. The data received after the overrun interrupt is gen-
erated (including the 9th data item) will become invalid and be discarded. However, if data is read
from the receive FIFO while the 9th data item is being received (before the interrupt is generated),
the 9th received data will be written in the receive FIFO as valid data. To perform transfer proper-
ly when the overrun interrupt has been generated, write "1" to SSPICR<RORIC> register, and then
read all data from the receive FIFO. Even if all the data is not read, data can be transmitted / re-
ceived if the receive FIFO has free space and the number of data to be transmitted does not exceed
the free space of the receive FIFO. Note that if the receive FIFO is not read (provided that the re-
ceive FIFO is not empty) within a certain 32-bit period (bit rate) after the overrun interrupt is
cleared, a time-out interrupt will be generated.
When the next data (9th data item) is received when the receive FIFO is already full, an overrun
Watermark level
1/2
Transmit (number of
empty locations)
Page 440
4
Burst length
Receive (number of fil-
led locations)
4
TMPM364F10FG