TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 192

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

SIO1CR<SIOS>
SCK1
SO1 pin
INTSIO1
interrupt
request
SIO1RDB
SIO1SR<SIOF>
SIO1SR<SEF>
SI1 pin
SIO1SR<TXF>
SIO1SR<TXERR>
SIO1TDB
SIO1SR<RXF>
SIO1CR<SIOINH>
pin output
Figure 14-15 Example of Transmit/Receive (Transmit) Error Processing
Writing transmit
data A
(b) Receive errors
contents, the received data is ignored while the SIO1SR<RXERR> is “1”.
A
Receive errors occur on the following situation. To protect SIO1RDB and the shift register
• Shift operation is finished before reading out received data from SIO1RDB at
A7 A6
D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
SIO1SR<RXF> is “1” in an external clock operation.
If receive error occurs, set the SIO1CR<SIOS> to “0” for reading the data that received
immediately before error occurence. And read the data from SIO1RDB. Data in shift
register (at errors occur) can be read by reading the SIO1RDB again.
When SIO1SR<RXERR> is cleared to “0” after reading the received data,
SIO1SR<RXF> is cleared to “0”.
After clearing SIO1CR<SIOS> to “0”, when 8-bit serial clock is input to
ceive operation is stopped. To restart the receive operation, confirm that
SIO1SR<SIOF> is cleared to “0”.
If the received error occurs, set the SIO1CR<SIOINH> to “1” for stopping the receive
operation immediately. In this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB reg-
ister and SIO1TDB register are initialized.
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Reading received
data D
Writing transmit
data B
Page 175
D
B
Start shift
operation
Reading received
data E
E
Start shift
operation
Reading received
data F
F
TMP86PM49UG
SCK1
Unknown
pin, re-