TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 224

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

SCL pin
SDA pin
PIN
INTSBI
interrupt request
16.6.3.2 When the MST is “0” (Slave mode)
Table 16-3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration
Figure 16-12 Termination of Data Transfer in Master Receiver Mode
after losing arbitration.
INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior
of INTSBI interrupt request and PIN after losing arbitration are shown in Table 16-3.
to low level. Either reading or writing from or to the SBIDBR or setting the PIN to “1” releases the SCL
pin after taking t
interrupt
request
INTSBI
In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an
When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICRB) is reset, and the SCL pin is set
PIN
word before the last data to be received. A serial bus interface circuit does not generate a clock pulse
for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when
the BC is set to “001” and read the data, PIN is set to “1” and generates a clock pulse for a 1-bit data
transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-level.
The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the trans-
mitter that data transfer is complete.
minate data transfer.
• At the end of acknowledge signal when the received slave address matches to the value set by the
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1-
After 1-bit data is received and an interrupt request has occurred, generate the stop condition to ter-
I2CAR
CALL”
When the Arbitration Lost Occurs during Trans-
mission of Slave Address as a Master
When the slave address matches the value set
by I2CAR, the PIN is cleared to "0" by generating
of INTSBI interrupt request. When the slave
address doesn't match the value set by I2CAR,
the PIN keeps "1".
D7
1
Clear ACK to "0"
before reading SBIDBR
LOW
D6
.
2
INTSBI interrupt request is generated at the termination of word data.
D5
3
D4
4
Page 207
D3
5
When the Arbitration Lost Occurs during Trans-
mission of Data as a Master Transmit Mode
PIN keeps "1" (PIN is not cleared to "0").
D2
6
D1
7
Set BC to "001"
before reading SBIDBR
D0
8
1
Acknowledge signal
sent to a transmitter
TMP86PM49UG