TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 48

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

2.3 Reset Circuit
2.3.1 External Reset Input
a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the
system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the
maximum 24/fc[s].
ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on.
The TMP86PM49UG has four types of reset generation procedures: An external reset input, an address trap reset,
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
RESET
Program counter
Stack pointer
General-purpose registers
Jump status flag
Zero flag
Carry flag
Half carry flag
Sign flag
Overflow flag
Interrupt master enable flag
Interrupt individual enable flags
Interrupt latches
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-
ized.
vector address stored at addresses FFFEH to FFFFH.
(W, A, B, C, D, E, H, L, IX, IY)
The
When the
When the
RESET
On-chip Hardware
VDD
RESET
RESET
pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
pin input goes high, the reset operation is released and the program execution starts at the
(IMF)
(PC)
(SP)
(CF)
(HF)
(SF)
(VF)
(EF)
(ZF)
(JF)
(IL)
Figure 2-15 Reset Circuit
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Initial Value
(FFFEH)
Internal reset
0
0
0
reset output
Malfunction
circuit
Page 31
Prescaler and divider of timing generator
Watchdog timer
Output latches of I/O ports
Control registers
RAM
On-chip Hardware
Watchdog timer reset
System clock reset
Address trap reset
Refer to I/O port circuitry
Refer to each of control
register
Not initialized
Initial Value
Enable
0
TMP86PM49UG