TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 217

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.5 I2C Bus Control
16.5.2 Number of transfer bits
16.5.3 Serial clock
16.5.3.1 Clock source
16.5.3.2 Clock synchronization
always executed in 8 bits. Other than these, the BC retains a specified value.
The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data.
Since the BC is cleared to “000” by a start condition, a slave address and direction bit transmissions are
pin in the master mode.
clock which is input from SCL pin.
pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a
high-level clock pulse.
In the master mode, a clock pulse for an acknowledge signal is not generated.
In the slave mode, a clock for a acknowledge signal is not counted.
The SCK (Bits2 to 0 in SBICRA) is used to select a maximum transfer frequency output from the SCL
Four or more machine cycles are required for both high and low levels of pulse width in the external
Note: Since the serial bus interface can not be used as the fast mode and the high-speed mode, do not set
In the I
Note 1: fc = High-frequency clock
Note 2: tcyc = 4/fc (in NORMAL mode, IDLE mode)
SCK as the frequency that is over 100 kHz.
t SCKL , t SCKH > 4 tcyc
t LOW = 2 /fc
t HIGH = 2 /fc + 8/fc
fscl = 1/( t LOW + t HIGH)
2
C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock
t SCKL
n
n
t HIGH
t SCKH
Figure 16-3 Clock Source
t LOW
Page 200
SCK (Bits2 to 0 in the SBICRA)
000
001
010
011
100
101
110
1/fscl
10
n
4
5
6
7
8
9
TMP86PM49UG