TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 204

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

SIO2CR<SIOS>
SIO2SR<SIOF>
SIO2SR<SEF>
SCK2
SI2 pin
SIO2SR<RXF>
INTSIO2
interrupt
request
SIO2RDB
pin
Figure 15-10 Example of Internal Clock and MSB Receive Mode
(3)
tion is finished. Then INTSIO2 interrupt request is generated after SIO2SR<RXERR> is set to “1”.
If received data is not read out from SIO2RDB receive error occurs immediately after shift opera-
Stopping the receive operation
There are two ways for stopping the receive operation.
A7
• The way of clearing SIO2CR<SIOS>.
• The way of setting SIO2CR<SIOINH>.
A6 A5 A4 A3 A2 A1
When SIO2CR<SIOS> is cleared to “0”, receive operation is stopped after all of the data is
finished to receive. When receive operation is finished, SIO2SR<SIOF> is cleared to “0”.
In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is
set to “1” by starting the next shift operation.
Receive operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In this case,
SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are initialized.
Start shift
operation
Automatic wait
A0
A
Writing transmit
data A
Page 187
B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Writing transmit
data B
B0
B
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86PM49UG
Writing transmit
data C
C